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Searched refs:CTLR_ENABLE_G1NS_BIT (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600_multichip.c72 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in set_gicd_dchipr_rt_owner()
108 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in set_gicd_chipr_n()
378 CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) { in gic600_multichip_init()
H A Dgicv3_main.c203 CTLR_ENABLE_G1NS_BIT, in gicv3_distif_init()
854 CTLR_ENABLE_G1NS_BIT, in gicv3_distif_init_restore()
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dcm3_system_reset.c137 a3700_gicd_ctlr_clear_bits(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1NS_BIT | in a3700_gic_reset()
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_psci_common.c298 CTLR_ENABLE_G1NS_BIT, in imx_system_reset()
/rk3399_ARM-atf/include/drivers/arm/
H A Dgicv3.h132 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT) macro