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Searched refs:CSR_UCCLKHCLKENABLES_ADDR (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_restore_sequence.c51 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_restore_sequence()
70 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_restore_sequence()
H A Dddrphy_phyinit_i_loadpieimage.c388 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_i_loadpieimage()
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/usercustom/
H A Dddrphy_phyinit_usercustom_saveretregs.c368 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_usercustom_saveretregs()
392 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), in ddrphy_phyinit_usercustom_saveretregs()
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_csr_all_cdefines.h987 #define CSR_UCCLKHCLKENABLES_ADDR 0x80U macro