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Searched refs:CRU_CLKSEL_CON (Results 1 – 13 of 13) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c336 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), in clk_cpul_set_rate()
338 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), in clk_cpul_set_rate()
340 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), in clk_cpul_set_rate()
347 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), in clk_cpul_set_rate()
349 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), in clk_cpul_set_rate()
352 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), in clk_cpul_set_rate()
354 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6), in clk_cpul_set_rate()
356 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7), in clk_cpul_set_rate()
384 mode = (mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) >> 14) & in rk3588_lpll_get_rate()
423 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x0060; in clk_scmi_cpul_get_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c371 ddr_data.clk_sel0 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(0)); in pm_plls_suspend()
372 ddr_data.clk_sel1 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(1)); in pm_plls_suspend()
373 ddr_data.clk_sel18 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(18)); in pm_plls_suspend()
374 ddr_data.clk_sel20 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(20)); in pm_plls_suspend()
375 ddr_data.clk_sel24 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(24)); in pm_plls_suspend()
376 ddr_data.clk_sel38 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(38)); in pm_plls_suspend()
383 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(0), in pm_plls_suspend()
387 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_suspend()
391 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(20), in pm_plls_suspend()
395 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(24), in pm_plls_suspend()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.c47 uint32_t cru_sel55 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(55)); in clear_glb_reset_status()
50 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55), in clear_glb_reset_status()
57 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55), in clear_glb_reset_status()
H A Dsoc.h35 #define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) macro
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c823 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x100) != 0) in clk_scmi_gpu_get_rate()
826 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x1f; in clk_scmi_gpu_get_rate()
827 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x00e0; in clk_scmi_gpu_get_rate()
873 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165), in clk_gpu_set_rate()
875 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165), in clk_gpu_set_rate()
882 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165), in clk_gpu_set_rate()
885 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165), in clk_gpu_set_rate()
887 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165), in clk_gpu_set_rate()
922 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(86)) & 0x8000) != 0) in clk_scmi_npu_get_rate()
925 div_src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(86)) & 0x07c; in clk_scmi_npu_get_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.h59 #define CRU_CLKSEL_CON 0x100 macro
60 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4)
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.h41 #define CRU_CLKSEL_CON 0x60 macro
42 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.h79 #define CRU_CLKSEL_CON 0x100 macro
80 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpm_pd_regs.c478 bcore0_cru_sel_con2 = mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2)); in pd_dsu_core_save()
479 bcore1_cru_sel_con2 = mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2)); in pd_dsu_core_save()
487 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), in pd_dsu_core_restore()
489 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), in pd_dsu_core_restore()
520 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2), in pd_dsu_core_restore()
522 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2), in pd_dsu_core_restore()
H A Dpmu.c1268 ddr_data.pmu1cru_clksel_con1 = mmio_read_32(PMU1CRU_BASE + CRU_CLKSEL_CON(1)); in pm_pll_suspend()
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h40 #define CRU_CLKSEL_CON(i) (0x100 + ((i) * 4)) macro
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.h45 #define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.h46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) macro