Searched refs:CPU_DEC_CCI_BASE_REG (Results 1 – 2 of 2) sorted by relevance
32 mmio_write_32(CPU_DEC_CCI_BASE_REG, MVEBU_CCI_BASE >> 20); in plat_marvell_interconnect_init()
223 #define CPU_DEC_CCI_BASE_REG (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0) macro