1 /*
2 * Copyright (C) 2024-2026, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <limits.h>
10 #include <stdint.h>
11
12 #include "clk-stm32-core.h"
13 #include <common/fdt_wrappers.h>
14 #include <drivers/clk.h>
15 #include <drivers/delay_timer.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <drivers/st/stm32mp2_clk.h>
18 #include <drivers/st/stm32mp_clkfunc.h>
19 #include <lib/mmio.h>
20 #include <lib/spinlock.h>
21 #include <lib/utils_def.h>
22 #include <libfdt.h>
23
24 #include <platform_def.h>
25
26 struct stm32_osci_dt_cfg {
27 unsigned long freq;
28 uint32_t drive;
29 bool bypass;
30 bool digbyp;
31 bool css;
32 };
33
34 struct stm32_pll_dt_cfg {
35 uint32_t src;
36 uint32_t frac;
37 uint32_t cfg[PLLCFG_NB];
38 uint32_t csg[PLLCSG_NB];
39 bool csg_enabled;
40 bool enabled;
41 };
42
43 struct stm32_clk_platdata {
44 uintptr_t rcc_base;
45 uint32_t nosci;
46 struct stm32_osci_dt_cfg *osci;
47 uint32_t npll;
48 struct stm32_pll_dt_cfg *pll;
49 uint32_t nflexgen;
50 uint32_t *flexgen;
51 uint32_t nbusclk;
52 uint32_t *busclk;
53 uint32_t nkernelclk;
54 uint32_t *kernelclk;
55 };
56
57 /* A35 Sub-System which manages its own PLL (PLL1) */
58 #define A35_SS_CHGCLKREQ 0x0000
59 #define A35_SS_PLL_FREQ1 0x0080
60 #define A35_SS_PLL_FREQ2 0x0090
61 #define A35_SS_PLL_ENABLE 0x00a0
62
63 #define A35_SS_CHGCLKREQ_ARM_CHGCLKREQ BIT(0)
64 #define A35_SS_CHGCLKREQ_ARM_CHGCLKACK BIT(1)
65 #define A35_SS_CHGCLKREQ_ARM_DIVSEL BIT(16)
66 #define A35_SS_CHGCLKREQ_ARM_DIVSELACK BIT(17)
67
68 #define A35_SS_PLL_FREQ1_FBDIV_MASK GENMASK(11, 0)
69 #define A35_SS_PLL_FREQ1_FBDIV_SHIFT 0
70 #define A35_SS_PLL_FREQ1_REFDIV_MASK GENMASK(21, 16)
71 #define A35_SS_PLL_FREQ1_REFDIV_SHIFT 16
72
73 #define A35_SS_PLL_FREQ2_POSTDIV1_MASK GENMASK(2, 0)
74 #define A35_SS_PLL_FREQ2_POSTDIV1_SHIFT 0
75 #define A35_SS_PLL_FREQ2_POSTDIV2_MASK GENMASK(5, 3)
76 #define A35_SS_PLL_FREQ2_POSTDIV2_SHIFT 3
77
78 #define A35_SS_PLL_ENABLE_PD BIT(0)
79 #define A35_SS_PLL_ENABLE_LOCKP BIT(1)
80 #define A35_SS_PLL_ENABLE_NRESET_SWPLL_FF BIT(2)
81
82 #define TIMEOUT_US_200MS U(200000)
83
84 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
85 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
86 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
87
88 /* PLL minimal frequencies for clock sources */
89 #define PLL_REFCLK_MIN UL(5000000)
90 #define PLL_FRAC_REFCLK_MIN UL(10000000)
91
92 #define XBAR_CHANNEL_NB 64
93
94 /* Warning, should be start to 1 */
95 enum clock {
96 _CK_0_MHZ,
97
98 /* ROOT CLOCKS */
99 _CK_HSI,
100 _CK_HSE,
101 _CK_MSI,
102 _CK_LSI,
103 _CK_LSE,
104 _I2SCKIN,
105 _SPDIFSYMB,
106 _CK_PLL1,
107 _CK_PLL2,
108 #if !STM32MP21
109 _CK_PLL3,
110 #endif /* !STM32MP21 */
111 _CK_PLL4,
112 _CK_PLL5,
113 _CK_PLL6,
114 _CK_PLL7,
115 _CK_PLL8,
116 _CK_HSE_RTC,
117 _CK_RTCCK,
118 _CK_ICN_HS_MCU,
119 _CK_ICN_SDMMC,
120 _CK_ICN_DDR,
121 _CK_ICN_HSL,
122 _CK_ICN_NIC,
123 _CK_ICN_LS_MCU,
124 _CK_FLEXGEN_07,
125 _CK_FLEXGEN_08,
126 _CK_FLEXGEN_09,
127 _CK_FLEXGEN_10,
128 _CK_FLEXGEN_11,
129 _CK_FLEXGEN_12,
130 _CK_FLEXGEN_13,
131 _CK_FLEXGEN_14,
132 _CK_FLEXGEN_15,
133 _CK_FLEXGEN_16,
134 _CK_FLEXGEN_17,
135 _CK_FLEXGEN_18,
136 _CK_FLEXGEN_19,
137 _CK_FLEXGEN_20,
138 _CK_FLEXGEN_21,
139 _CK_FLEXGEN_22,
140 _CK_FLEXGEN_23,
141 _CK_FLEXGEN_24,
142 _CK_FLEXGEN_25,
143 _CK_FLEXGEN_26,
144 _CK_FLEXGEN_27,
145 _CK_FLEXGEN_28,
146 _CK_FLEXGEN_29,
147 _CK_FLEXGEN_30,
148 _CK_FLEXGEN_31,
149 _CK_FLEXGEN_32,
150 _CK_FLEXGEN_33,
151 _CK_FLEXGEN_34,
152 _CK_FLEXGEN_35,
153 _CK_FLEXGEN_36,
154 _CK_FLEXGEN_37,
155 _CK_FLEXGEN_38,
156 _CK_FLEXGEN_39,
157 _CK_FLEXGEN_40,
158 _CK_FLEXGEN_41,
159 _CK_FLEXGEN_42,
160 _CK_FLEXGEN_43,
161 _CK_FLEXGEN_44,
162 _CK_FLEXGEN_45,
163 _CK_FLEXGEN_46,
164 _CK_FLEXGEN_47,
165 _CK_FLEXGEN_48,
166 _CK_FLEXGEN_49,
167 _CK_FLEXGEN_50,
168 _CK_FLEXGEN_51,
169 _CK_FLEXGEN_52,
170 _CK_FLEXGEN_53,
171 _CK_FLEXGEN_54,
172 _CK_FLEXGEN_55,
173 _CK_FLEXGEN_56,
174 _CK_FLEXGEN_57,
175 _CK_FLEXGEN_58,
176 _CK_FLEXGEN_59,
177 _CK_FLEXGEN_60,
178 _CK_FLEXGEN_61,
179 _CK_FLEXGEN_62,
180 _CK_FLEXGEN_63,
181 _CK_ICN_APB1,
182 _CK_ICN_APB2,
183 _CK_ICN_APB3,
184 _CK_ICN_APB4,
185 #if STM32MP21
186 _CK_ICN_APB5,
187 #endif /* STM32MP21 */
188 _CK_ICN_APBDBG,
189 _CK_BKPSRAM,
190 _CK_BSEC,
191 _CK_CRC,
192 _CK_CRYP1,
193 _CK_CRYP2,
194 _CK_DDR,
195 _CK_DDRCAPB,
196 _CK_DDRCP,
197 _CK_DDRPHYC,
198 _CK_FMC,
199 _CK_GPIOA,
200 _CK_GPIOB,
201 _CK_GPIOC,
202 _CK_GPIOD,
203 _CK_GPIOE,
204 _CK_GPIOF,
205 _CK_GPIOG,
206 _CK_GPIOH,
207 _CK_GPIOI,
208 #if !STM32MP21
209 _CK_GPIOJ,
210 _CK_GPIOK,
211 #endif /* !STM32MP21 */
212 _CK_GPIOZ,
213 #if STM32MP21
214 _CK_HASH1,
215 _CK_HASH2,
216 #else /* STM32MP21 */
217 _CK_HASH,
218 #endif /* STM32MP21 */
219 _CK_I2C1,
220 _CK_I2C2,
221 #if !STM32MP23
222 _CK_I2C3,
223 #endif /* !STM32MP23 */
224 #if STM32MP25
225 _CK_I2C4,
226 _CK_I2C5,
227 _CK_I2C6,
228 #endif /* STM32MP25 */
229 #if !STM32MP21
230 _CK_I2C7,
231 _CK_I2C8,
232 #endif /* !STM32MP21 */
233 _CK_IWDG1,
234 _CK_IWDG2,
235 _CK_OSPI1,
236 #if !STM32MP21
237 _CK_OSPI2,
238 _CK_OSPIIOM,
239 #endif /* !STM32MP21 */
240 _CK_PKA,
241 _CK_RETRAM,
242 #if STM32MP21
243 _CK_RNG1,
244 _CK_RNG2,
245 #else /* STM32MP21 */
246 _CK_RNG,
247 #endif /* STM32MP21 */
248 _CK_RTC,
249 _CK_SAES,
250 _CK_SDMMC1,
251 _CK_SDMMC2,
252 _CK_SRAM1,
253 #if !STM32MP21
254 _CK_SRAM2,
255 #endif /* !STM32MP21 */
256 _CK_STGEN,
257 _CK_SYSCPU1,
258 _CK_SYSDBG,
259 _CK_SYSRAM,
260 _CK_UART4,
261 _CK_UART5,
262 _CK_UART7,
263 #if STM32MP25
264 _CK_UART8,
265 _CK_UART9,
266 #endif /* STM32MP25 */
267 _CK_USART1,
268 _CK_USART2,
269 _CK_USART3,
270 _CK_USART6,
271 #if STM32MP21
272 _CK_USBHEHCI,
273 _CK_USBHOHCI,
274 #else /* STM32MP21 */
275 _CK_USB2EHCI,
276 _CK_USB2OHCI,
277 #endif /* STM32MP21 */
278 _CK_USB2PHY1,
279 _CK_USB2PHY2,
280 #if !STM32MP21
281 _CK_USB3DR,
282 _CK_USB3PCIEPHY,
283 _CK_USBTC,
284 #endif /* !STM32MP21 */
285 _CK_BUS_RISAF4,
286
287 CK_LAST
288 };
289
290 static const uint16_t muxsel_src[] = {
291 _CK_HSI, _CK_HSE, _CK_MSI, _CK_0_MHZ
292 };
293
294 static const uint16_t xbarsel_src[] = {
295 _CK_PLL4, _CK_PLL5, _CK_PLL6, _CK_PLL7, _CK_PLL8,
296 _CK_HSI, _CK_HSE, _CK_MSI, _CK_HSI, _CK_HSE, _CK_MSI,
297 _SPDIFSYMB, _I2SCKIN, _CK_LSI, _CK_LSE
298 };
299
300 static const uint16_t rtc_src[] = {
301 _CK_0_MHZ, _CK_LSE, _CK_LSI, _CK_HSE_RTC
302 };
303
304 static const uint16_t usb2phy1_src[] = {
305 _CK_FLEXGEN_57, _CK_HSE
306 };
307
308 static const uint16_t usb2phy2_src[] = {
309 _CK_FLEXGEN_58, _CK_HSE
310 };
311
312 #if !STM32MP21
313 static const uint16_t usb3pciphy_src[] = {
314 _CK_FLEXGEN_34, _CK_HSE
315 };
316
317 static const uint16_t d3per_src[] = {
318 _CK_MSI, _CK_LSI, _CK_LSE
319 };
320 #endif /* !STM32MP21 */
321
322 #define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\
323 .id_parents = src,\
324 .num_parents = ARRAY_SIZE(src),\
325 .mux = &(struct mux_cfg) {\
326 .offset = (_offset),\
327 .shift = (_shift),\
328 .width = (_witdh),\
329 .bitrdy = UINT8_MAX,\
330 },\
331 }
332
333 static const struct parent_cfg parent_mp2[] = {
334 MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2),
335 MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2),
336 MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2),
337 MUX_CONF(MUX_MUXSEL3, muxsel_src, RCC_MUXSELCFGR, 12, 2),
338 MUX_CONF(MUX_MUXSEL4, muxsel_src, RCC_MUXSELCFGR, 16, 2),
339 MUX_CONF(MUX_MUXSEL5, muxsel_src, RCC_MUXSELCFGR, 20, 2),
340 MUX_CONF(MUX_MUXSEL6, muxsel_src, RCC_MUXSELCFGR, 24, 2),
341 MUX_CONF(MUX_MUXSEL7, muxsel_src, RCC_MUXSELCFGR, 28, 2),
342 MUX_CONF(MUX_XBARSEL, xbarsel_src, RCC_XBAR0CFGR, 0, 4),
343 MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
344 MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
345 MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
346 #if !STM32MP21
347 MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
348 MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2),
349 #endif /* !STM32MP21 */
350 };
351
352 /* GATES */
353 enum enum_gate_cfg {
354 GATE_ZERO, /* reserved for no gate */
355 GATE_LSE,
356 GATE_RTCCK,
357 GATE_LSI,
358 GATE_HSI,
359 GATE_MSI,
360 GATE_HSE,
361 GATE_LSI_RDY,
362 GATE_MSI_RDY,
363 GATE_LSE_RDY,
364 GATE_HSE_RDY,
365 GATE_HSI_RDY,
366 GATE_SYSRAM,
367 GATE_RETRAM,
368 GATE_SRAM1,
369 #if !STM32MP21
370 GATE_SRAM2,
371 #endif /* !STM32MP21 */
372
373 GATE_DDRPHYC,
374 GATE_SYSCPU1,
375 GATE_CRC,
376 #if !STM32MP21
377 GATE_OSPIIOM,
378 #endif /* !STM32MP21 */
379 GATE_BKPSRAM,
380 #if STM32MP21
381 GATE_HASH1,
382 GATE_HASH2,
383 GATE_RNG1,
384 GATE_RNG2,
385 #else /* STM32MP21 */
386 GATE_HASH,
387 GATE_RNG,
388 #endif /* STM32MP21 */
389 GATE_CRYP1,
390 GATE_CRYP2,
391 GATE_SAES,
392 GATE_PKA,
393
394 GATE_GPIOA,
395 GATE_GPIOB,
396 GATE_GPIOC,
397 GATE_GPIOD,
398 GATE_GPIOE,
399 GATE_GPIOF,
400 GATE_GPIOG,
401 GATE_GPIOH,
402 GATE_GPIOI,
403 #if !STM32MP21
404 GATE_GPIOJ,
405 GATE_GPIOK,
406 #endif /* !STM32MP21 */
407 GATE_GPIOZ,
408 GATE_RTC,
409
410 GATE_DDRCP,
411
412 /* WARNING 2 CLOCKS FOR ONE GATE */
413 #if STM32MP21
414 GATE_USBHOHCI,
415 GATE_USBHEHCI,
416 #else /* STM32MP21 */
417 GATE_USB2OHCI,
418 GATE_USB2EHCI,
419 #endif /* STM32MP21 */
420
421 #if !STM32MP21
422 GATE_USB3DR,
423 #endif /* !STM32MP21 */
424
425 GATE_BSEC,
426 GATE_IWDG1,
427 GATE_IWDG2,
428
429 GATE_DBG,
430 GATE_DDRCAPB,
431 GATE_DDR,
432
433 GATE_USART2,
434 GATE_UART4,
435 GATE_USART3,
436 GATE_UART5,
437 GATE_I2C1,
438 GATE_I2C2,
439 #if !STM32MP23
440 GATE_I2C3,
441 #endif /* !STM32MP23 */
442 #if STM32MP25
443 GATE_I2C5,
444 GATE_I2C4,
445 GATE_I2C6,
446 #endif /* STM32MP25 */
447 #if !STM32MP21
448 GATE_I2C7,
449 #endif /* !STM32MP21 */
450 GATE_USART1,
451 GATE_USART6,
452 GATE_UART7,
453 #if STM32MP25
454 GATE_UART8,
455 GATE_UART9,
456 #endif /* STM32MP25 */
457 GATE_STGEN,
458 #if !STM32MP21
459 GATE_USB3PCIEPHY,
460 GATE_USBTC,
461 GATE_I2C8,
462 #endif /* !STM32MP21 */
463 GATE_OSPI1,
464 #if !STM32MP21
465 GATE_OSPI2,
466 #endif /* !STM32MP21 */
467 GATE_FMC,
468 GATE_SDMMC1,
469 GATE_SDMMC2,
470 GATE_USB2PHY1,
471 GATE_USB2PHY2,
472 LAST_GATE
473 };
474
475 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\
476 .offset = (_offset),\
477 .bit_idx = (_bit_idx),\
478 .set_clr = (_offset_clr),\
479 }
480
481 static const struct gate_cfg gates_mp2[LAST_GATE] = {
482 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
483 #if STM32MP21
484 GATE_CFG(GATE_LSI, RCC_LSICR, 0, 0),
485 #else /* STM32MP21 */
486 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0),
487 #endif /* STM32MP21 */
488 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
489 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
490 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
491 #if STM32MP21
492 GATE_CFG(GATE_MSI, RCC_OCENSETR, 2, 0),
493 #else /* STM32MP21 */
494 GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0),
495 #endif /* STM32MP21 */
496
497 #if STM32MP21
498 GATE_CFG(GATE_LSI_RDY, RCC_LSICR, 1, 0),
499 #else /* STM32MP21 */
500 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0),
501 #endif /* STM32MP21 */
502 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
503 #if STM32MP21
504 GATE_CFG(GATE_MSI_RDY, RCC_OCRDYR, 2, 0),
505 #else /* STM32MP21 */
506 GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0),
507 #endif /* STM32MP21 */
508 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
509 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
510 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0),
511 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0),
512 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0),
513 #if !STM32MP21
514 GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0),
515 #endif /* !STM32MP21 */
516 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0),
517 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0),
518 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
519 #if !STM32MP21
520 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
521 #endif /* !STM32MP21 */
522 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0),
523 #if STM32MP21
524 GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0),
525 GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0),
526 GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0),
527 GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0),
528 #else /* STM32MP21 */
529 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
530 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
531 #endif /* STM32MP21 */
532 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
533 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
534 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
535 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
536 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0),
537 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0),
538 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0),
539 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0),
540 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0),
541 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0),
542 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0),
543 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0),
544 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0),
545 #if !STM32MP21
546 GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0),
547 GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0),
548 #endif /* !STM32MP21 */
549 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0),
550 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0),
551 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0),
552
553 /* WARNING 2 CLOCKS FOR ONE GATE */
554 #if STM32MP21
555 GATE_CFG(GATE_USBHOHCI, RCC_USBHCFGR, 1, 0),
556 GATE_CFG(GATE_USBHEHCI, RCC_USBHCFGR, 1, 0),
557 #else /* STM32MP21 */
558 GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0),
559 GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0),
560 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
561 #endif /* STM32MP21 */
562 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0),
563 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
564 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
565 GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0),
566 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0),
567 GATE_CFG(GATE_DDR, RCC_DDRCFGR, 1, 0),
568 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
569 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
570 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
571 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
572 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
573 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
574 #if !STM32MP23
575 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
576 #endif /* !STM32MP23 */
577 #if STM32MP25
578 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
579 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
580 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
581 #endif /* STM32MP25 */
582 #if !STM32MP21
583 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
584 #endif /* !STM32MP21 */
585 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
586 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
587 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
588 #if STM32MP25
589 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
590 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
591 #endif /* STM32MP25 */
592 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
593 #if !STM32MP21
594 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
595 GATE_CFG(GATE_USBTC, RCC_UCPDCFGR, 1, 0),
596 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
597 #endif /* !STM32MP21 */
598 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
599 #if !STM32MP21
600 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0),
601 #endif /* !STM32MP21 */
602 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0),
603 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
604 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
605 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
606 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
607 };
608
609 static const struct clk_div_table apb_div_table[] = {
610 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, { 4, 16 },
611 { 5, 16 }, { 6, 16 }, { 7, 16 }, { 0 },
612 };
613
614 #undef DIV_CFG
615 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\
616 .offset = _offset,\
617 .shift = _shift,\
618 .width = _width,\
619 .flags = _flags,\
620 .table = _table,\
621 .bitrdy = _bitrdy,\
622 }
623
624 static const struct div_cfg dividers_mp2[] = {
625 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
626 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
627 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
628 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
629 #if STM32MP21
630 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
631 #endif /* STM32MP21 */
632 DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
633 DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
634 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
635 };
636
637 enum stm32_osc {
638 OSC_HSI,
639 OSC_HSE,
640 OSC_MSI,
641 OSC_LSI,
642 OSC_LSE,
643 OSC_I2SCKIN,
644 OSC_SPDIFSYMB,
645 NB_OSCILLATOR
646 };
647
648 #define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\
649 .offset = (_offset),\
650 .bit_byp = (_bit_byp),\
651 .bit_digbyp = (_bit_digbyp),\
652 }
653
654 #define CSS(_offset, _bit_css) &(struct stm32_clk_css){\
655 .offset = (_offset),\
656 .bit_css = (_bit_css),\
657 }
658
659 #define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\
660 .offset = (_offset),\
661 .drv_shift = (_shift),\
662 .drv_width = (_width),\
663 .drv_default = (_default),\
664 }
665
666 #define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \
667 [(idx_osc)] = (struct clk_oscillator_data){\
668 .name = (_name),\
669 .id_clk = (_id),\
670 .gate_id = (_gate_id),\
671 .gate_rdy_id = (_gate_rdy_id),\
672 .bypass = (_bypass),\
673 .css = (_css),\
674 .drive = (_drive),\
675 }
676
677 static struct clk_oscillator_data stm32mp2_osc_data[] = {
678 OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
679 NULL, NULL, NULL),
680
681 OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY,
682 NULL, NULL, NULL),
683
684 OSCILLATOR(OSC_MSI, _CK_MSI, "clk-msi", GATE_MSI, GATE_MSI_RDY,
685 NULL, NULL, NULL),
686
687 OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY,
688 BYPASS(RCC_OCENSETR, 10, 7),
689 CSS(RCC_OCENSETR, 11),
690 NULL),
691
692 OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY,
693 BYPASS(RCC_BDCR, 1, 3),
694 CSS(RCC_BDCR, 8),
695 DRIVE(RCC_BDCR, 4, 2, 2)),
696
697 OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE,
698 NULL, NULL, NULL),
699
700 OSCILLATOR(OSC_SPDIFSYMB, _SPDIFSYMB, "spdif_symb", NO_GATE, NO_GATE,
701 NULL, NULL, NULL),
702 };
703
704 #ifdef IMAGE_BL2
clk_stm32_get_oscillator_name(enum stm32_osc id)705 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
706 {
707 if (id < NB_OSCILLATOR) {
708 return stm32mp2_osc_data[id].name;
709 }
710
711 return NULL;
712 }
713
714 #if !STM32MP_M33_TDCID
clk_oscillator_set_bypass(struct stm32_clk_priv * priv,int id,bool digbyp,bool bypass)715 static void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id,
716 bool digbyp, bool bypass)
717 {
718 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
719
720 struct stm32_clk_bypass *bypass_data = osc_data->bypass;
721 uintptr_t address;
722
723 if (bypass_data == NULL) {
724 return;
725 }
726
727 address = priv->base + bypass_data->offset;
728
729 if (digbyp) {
730 mmio_setbits_32(address, BIT(bypass_data->bit_digbyp));
731 }
732
733 if (bypass || digbyp) {
734 mmio_setbits_32(address, BIT(bypass_data->bit_byp));
735 }
736 }
737
clk_oscillator_set_css(struct stm32_clk_priv * priv,int id,bool css)738 static void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id,
739 bool css)
740 {
741 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
742
743 struct stm32_clk_css *css_data = osc_data->css;
744 uintptr_t address;
745
746 if (css_data == NULL) {
747 return;
748 }
749
750 address = priv->base + css_data->offset;
751
752 if (css) {
753 mmio_setbits_32(address, BIT(css_data->bit_css));
754 }
755 }
756
clk_oscillator_set_drive(struct stm32_clk_priv * priv,int id,uint8_t lsedrv)757 static void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id,
758 uint8_t lsedrv)
759 {
760 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
761
762 struct stm32_clk_drive *drive_data = osc_data->drive;
763 uintptr_t address;
764 uint32_t mask;
765 uint32_t value;
766
767 if (drive_data == NULL) {
768 return;
769 }
770
771 address = priv->base + drive_data->offset;
772
773 mask = (BIT(drive_data->drv_width) - 1U) << drive_data->drv_shift;
774
775 /*
776 * Warning: not recommended to switch directly from "high drive"
777 * to "medium low drive", and vice-versa.
778 */
779 value = (mmio_read_32(address) & mask) >> drive_data->drv_shift;
780
781 while (value != lsedrv) {
782 if (value > lsedrv) {
783 value--;
784 } else {
785 value++;
786 }
787
788 mmio_clrsetbits_32(address, mask, value << drive_data->drv_shift);
789 }
790 }
791
clk_oscillator_wait_ready(struct stm32_clk_priv * priv,int id,bool ready_on)792 static int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id,
793 bool ready_on)
794 {
795 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
796
797 return _clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, ready_on);
798 }
799
clk_oscillator_wait_ready_on(struct stm32_clk_priv * priv,int id)800 static int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id)
801 {
802 return clk_oscillator_wait_ready(priv, id, true);
803 }
804 #endif /* !STM32MP_M33_TDCID */
805 #endif /* IMAGE_BL2 */
806
clk_stm32_osc_recalc_rate(struct stm32_clk_priv * priv,int id,unsigned long prate)807 static unsigned long clk_stm32_osc_recalc_rate(struct stm32_clk_priv *priv,
808 int id, unsigned long prate)
809 {
810 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
811
812 return osc_data->frequency;
813 };
814
clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv * priv,int id)815 static bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id)
816 {
817 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
818
819 if (osc_data->frequency == 0UL) {
820 return true;
821 }
822
823 return _clk_stm32_gate_is_enabled(priv, osc_data->gate_id);
824
825 }
826
clk_stm32_osc_gate_enable(struct stm32_clk_priv * priv,int id)827 static int __maybe_unused clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id)
828 {
829 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
830
831 if (osc_data->frequency == 0UL) {
832 return 0;
833 }
834
835 _clk_stm32_gate_enable(priv, osc_data->gate_id);
836
837 if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, true) != 0U) {
838 ERROR("%s: %s (%d)\n", __func__, osc_data->name, __LINE__);
839 panic();
840 }
841
842 return 0;
843 }
844
clk_stm32_osc_gate_disable(struct stm32_clk_priv * priv,int id)845 static void __maybe_unused clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id)
846 {
847 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
848
849 if (osc_data->frequency == 0UL) {
850 return;
851 }
852
853 _clk_stm32_gate_disable(priv, osc_data->gate_id);
854
855 if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, false) != 0U) {
856 ERROR("%s: %s (%d)\n", __func__, osc_data->name, __LINE__);
857 panic();
858 }
859 }
860
clk_stm32_get_dt_oscillator_frequency(const char * name)861 static unsigned long clk_stm32_get_dt_oscillator_frequency(const char *name)
862 {
863 void *fdt = NULL;
864 int node = 0;
865 int subnode = 0;
866
867 if (fdt_get_address(&fdt) == 0) {
868 panic();
869 }
870
871 node = fdt_path_offset(fdt, "/clocks");
872 if (node < 0) {
873 return 0UL;
874 }
875
876 fdt_for_each_subnode(subnode, fdt, node) {
877 const char *cchar = NULL;
878 const fdt32_t *cuint = NULL;
879 int ret = 0;
880
881 cchar = fdt_get_name(fdt, subnode, &ret);
882 if (cchar == NULL) {
883 continue;
884 }
885
886 if (strncmp(cchar, name, (size_t)ret) ||
887 fdt_get_status(subnode) == DT_DISABLED) {
888 continue;
889 }
890
891 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
892 if (cuint == NULL) {
893 return 0UL;
894 }
895
896 return fdt32_to_cpu(*cuint);
897 }
898
899 return 0UL;
900 }
901
clk_stm32_osc_init(struct stm32_clk_priv * priv,int id)902 static void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id)
903 {
904 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
905 const char *name = osc_data->name;
906
907 osc_data->frequency = clk_stm32_get_dt_oscillator_frequency(name);
908 }
909
910 static struct stm32_clk_ops clk_stm32_osc_ops = {
911 .recalc_rate = clk_stm32_osc_recalc_rate,
912 .is_enabled = clk_stm32_osc_gate_is_enabled,
913 #if !STM32MP_M33_TDCID
914 .enable = clk_stm32_osc_gate_enable,
915 .disable = clk_stm32_osc_gate_disable,
916 #endif
917 .init = clk_stm32_osc_init,
918 };
919
920 static struct stm32_clk_ops clk_stm32_osc_nogate_ops = {
921 .recalc_rate = clk_stm32_osc_recalc_rate,
922 .init = clk_stm32_osc_init,
923 };
924
925 enum pll_id {
926 _PLL1,
927 _PLL2,
928 _PLL3,
929 _PLL4,
930 _PLL5,
931 _PLL6,
932 _PLL7,
933 _PLL8,
934 _PLL_NB
935 };
936
937 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */
938 #define RCC_OFFSET_PLLXCFGR1 0x00
939 #define RCC_OFFSET_PLLXCFGR2 0x04
940 #define RCC_OFFSET_PLLXCFGR3 0x08
941 #define RCC_OFFSET_PLLXCFGR4 0x0C
942 #define RCC_OFFSET_PLLXCFGR5 0x10
943 #define RCC_OFFSET_PLLXCFGR6 0x18
944 #define RCC_OFFSET_PLLXCFGR7 0x1C
945
946 struct stm32_clk_pll {
947 uint16_t clk_id;
948 uint16_t reg_pllxcfgr1;
949 };
950
951 #define CLK_PLL_CFG(_idx, _clk_id, _reg)\
952 [(_idx)] = {\
953 .clk_id = (_clk_id),\
954 .reg_pllxcfgr1 = (_reg),\
955 }
956
957 static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = {
958 CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
959 CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1),
960 #if !STM32MP21
961 CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1),
962 #endif /* !STM32MP21 */
963 CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1),
964 CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1),
965 CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1),
966 CLK_PLL_CFG(_PLL7, _CK_PLL7, RCC_PLL7CFGR1),
967 CLK_PLL_CFG(_PLL8, _CK_PLL8, RCC_PLL8CFGR1),
968 };
969
clk_stm32_pll_data(unsigned int idx)970 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
971 {
972 return &stm32mp2_clk_pll[idx];
973 }
974
clk_get_pll_fvco(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,unsigned long prate)975 static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,
976 const struct stm32_clk_pll *pll,
977 unsigned long prate)
978 {
979 unsigned long refclk, fvco;
980 uint32_t fracin, fbdiv, refdiv;
981 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
982 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
983 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
984
985 refclk = prate;
986
987 fracin = mmio_read_32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK;
988 fbdiv = (mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >>
989 RCC_PLLxCFGR2_FBDIV_SHIFT;
990 refdiv = mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK;
991
992 if (fracin != 0U) {
993 uint64_t numerator, denominator;
994
995 numerator = ((uint64_t)fbdiv << 24) + fracin;
996 numerator = refclk * numerator;
997 denominator = (uint64_t)refdiv << 24;
998 fvco = (unsigned long)(numerator / denominator);
999 } else {
1000 fvco = (unsigned long)(refclk * fbdiv / refdiv);
1001 }
1002
1003 return fvco;
1004 }
1005
1006 struct stm32_pll_cfg {
1007 uint16_t pll_id;
1008 };
1009
_clk_stm32_pll_is_enabled(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1010 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1011 {
1012 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1013
1014 return ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLEN) != 0U);
1015 }
1016
_clk_stm32_pll_set_on(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1017 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1018 {
1019 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1020
1021 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
1022 }
1023
_clk_stm32_pll_set_off(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1024 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1025 {
1026 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1027
1028 /* Stop PLL */
1029 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
1030 }
1031
_clk_stm32_pll_wait_ready_on(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1032 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,
1033 const struct stm32_clk_pll *pll)
1034 {
1035 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1036 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1037
1038 /* Wait PLL lock */
1039 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) == 0U) {
1040 if (timeout_elapsed(timeout)) {
1041 ERROR("PLL%d start failed @ 0x%x: 0x%x\n",
1042 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcfgr1,
1043 mmio_read_32(pllxcfgr1));
1044 return -ETIMEDOUT;
1045 }
1046 }
1047
1048 return 0;
1049 }
1050
_clk_stm32_pll_wait_ready_off(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1051 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,
1052 const struct stm32_clk_pll *pll)
1053 {
1054 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1055 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1056
1057 /* Wait PLL stopped */
1058 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) != 0U) {
1059 if (timeout_elapsed(timeout)) {
1060 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n",
1061 pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1));
1062 return -ETIMEDOUT;
1063 }
1064 }
1065
1066 return 0;
1067 }
1068
_clk_stm32_pll_enable(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1069 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1070 {
1071 if (_clk_stm32_pll_is_enabled(priv, pll)) {
1072 return 0;
1073 }
1074
1075 _clk_stm32_pll_set_on(priv, pll);
1076
1077 return _clk_stm32_pll_wait_ready_on(priv, pll);
1078 }
1079
_clk_stm32_pll_disable(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)1080 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1081 {
1082 if (!_clk_stm32_pll_is_enabled(priv, pll)) {
1083 return;
1084 }
1085
1086 _clk_stm32_pll_set_off(priv, pll);
1087
1088 _clk_stm32_pll_wait_ready_off(priv, pll);
1089 }
1090
clk_stm32_pll_is_enabled(struct stm32_clk_priv * priv,int id)1091 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id)
1092 {
1093 const struct clk_stm32 *clk = _clk_get(priv, id);
1094 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1095 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
1096
1097 return _clk_stm32_pll_is_enabled(priv, pll);
1098 }
1099
clk_stm32_pll_enable(struct stm32_clk_priv * priv,int id)1100 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id)
1101 {
1102 const struct clk_stm32 *clk = _clk_get(priv, id);
1103 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1104 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
1105
1106 return _clk_stm32_pll_enable(priv, pll);
1107 }
1108
clk_stm32_pll_disable(struct stm32_clk_priv * priv,int id)1109 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id)
1110 {
1111 const struct clk_stm32 *clk = _clk_get(priv, id);
1112 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1113 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
1114
1115 _clk_stm32_pll_disable(priv, pll);
1116 }
1117
clk_stm32_pll_recalc_rate(struct stm32_clk_priv * priv,int id,unsigned long prate)1118 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
1119 unsigned long prate)
1120 {
1121 const struct clk_stm32 *clk = _clk_get(priv, id);
1122 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
1123 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
1124 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1125 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
1126 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
1127 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
1128 unsigned long dfout;
1129 uint32_t postdiv1, postdiv2;
1130
1131 postdiv1 = mmio_read_32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK;
1132 postdiv2 = mmio_read_32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK;
1133
1134 if ((mmio_read_32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) != 0U) {
1135 dfout = prate;
1136 } else {
1137 if ((postdiv1 == 0U) || (postdiv2 == 0U)) {
1138 dfout = prate;
1139 } else {
1140 dfout = clk_get_pll_fvco(priv, pll, prate) / (postdiv1 * postdiv2);
1141 }
1142 }
1143
1144 return dfout;
1145 }
1146
1147 static const struct stm32_clk_ops clk_stm32_pll_ops = {
1148 .recalc_rate = clk_stm32_pll_recalc_rate,
1149 .enable = clk_stm32_pll_enable,
1150 .disable = clk_stm32_pll_disable,
1151 .is_enabled = clk_stm32_pll_is_enabled,
1152 };
1153
1154 #define CLK_PLL(idx, _idx, _parent, _pll_id, _flags)[idx] = {\
1155 .binding = _idx,\
1156 .parent = _parent,\
1157 .flags = (_flags),\
1158 .clock_cfg = &(struct stm32_pll_cfg) {\
1159 .pll_id = _pll_id,\
1160 },\
1161 .ops = STM32_PLL_OPS,\
1162 }
1163
clk_get_pll1_fvco(unsigned long refclk)1164 static unsigned long clk_get_pll1_fvco(unsigned long refclk)
1165 {
1166 uintptr_t pll_freq1_reg = A35SSC_BASE + A35_SS_PLL_FREQ1;
1167 uint32_t reg, fbdiv, refdiv;
1168
1169 reg = mmio_read_32(pll_freq1_reg);
1170
1171 fbdiv = (reg & A35_SS_PLL_FREQ1_FBDIV_MASK) >> A35_SS_PLL_FREQ1_FBDIV_SHIFT;
1172 refdiv = (reg & A35_SS_PLL_FREQ1_REFDIV_MASK) >> A35_SS_PLL_FREQ1_REFDIV_SHIFT;
1173
1174 return (unsigned long)(refclk * fbdiv / refdiv);
1175 }
1176
clk_stm32_pll1_recalc_rate(struct stm32_clk_priv * priv,int id,unsigned long prate)1177 static unsigned long clk_stm32_pll1_recalc_rate(struct stm32_clk_priv *priv,
1178 int id, unsigned long prate)
1179 {
1180 uintptr_t pll_freq2_reg = A35SSC_BASE + A35_SS_PLL_FREQ2;
1181 uint32_t postdiv1, postdiv2;
1182 unsigned long dfout;
1183
1184 postdiv1 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV1_MASK) >>
1185 A35_SS_PLL_FREQ2_POSTDIV1_SHIFT;
1186 postdiv2 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV2_MASK) >>
1187 A35_SS_PLL_FREQ2_POSTDIV2_SHIFT;
1188
1189 if ((postdiv1 == 0U) || (postdiv2 == 0U)) {
1190 dfout = prate;
1191 } else {
1192 dfout = clk_get_pll1_fvco(prate) / (postdiv1 * postdiv2);
1193 }
1194
1195 return dfout;
1196 }
1197
1198 static const struct stm32_clk_ops clk_stm32_pll1_ops = {
1199 .recalc_rate = clk_stm32_pll1_recalc_rate,
1200 };
1201
1202 #define CLK_PLL1(idx, _idx, _parent, _pll_id, _flags)[idx] = {\
1203 .binding = _idx,\
1204 .parent = _parent,\
1205 .flags = (_flags),\
1206 .clock_cfg = &(struct stm32_pll_cfg) {\
1207 .pll_id = _pll_id,\
1208 },\
1209 .ops = STM32_PLL1_OPS,\
1210 }
1211
1212 struct stm32_clk_flexgen_cfg {
1213 uint8_t id;
1214 };
1215
clk_flexgen_recalc(struct stm32_clk_priv * priv,int idx,unsigned long prate)1216 static unsigned long clk_flexgen_recalc(struct stm32_clk_priv *priv, int idx,
1217 unsigned long prate)
1218 {
1219 const struct clk_stm32 *clk = _clk_get(priv, idx);
1220 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
1221 uintptr_t rcc_base = priv->base;
1222 uint32_t prediv, findiv;
1223 uint8_t channel = cfg->id;
1224 unsigned long freq = prate;
1225
1226 prediv = mmio_read_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel)) &
1227 RCC_PREDIVxCFGR_PREDIVx_MASK;
1228 findiv = mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) &
1229 RCC_FINDIVxCFGR_FINDIVx_MASK;
1230
1231 if (freq == 0UL) {
1232 return 0U;
1233 }
1234
1235 switch (prediv) {
1236 case 0x0:
1237 case 0x1:
1238 case 0x3:
1239 case 0x3FF:
1240 break;
1241
1242 default:
1243 ERROR("Unsupported PREDIV value (%x)\n", prediv);
1244 panic();
1245 break;
1246 }
1247
1248 freq /= (prediv + 1U);
1249 freq /= (findiv + 1U);
1250
1251 return freq;
1252 }
1253
clk_flexgen_get_parent(struct stm32_clk_priv * priv,int idx)1254 static int clk_flexgen_get_parent(struct stm32_clk_priv *priv, int idx)
1255 {
1256 const struct clk_stm32 *clk = _clk_get(priv, idx);
1257 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
1258 uint32_t sel;
1259 uint32_t address;
1260 uintptr_t rcc_base = priv->base;
1261
1262 address = RCC_XBAR0CFGR + (cfg->id * 4);
1263
1264 sel = mmio_read_32(rcc_base + address) & RCC_XBARxCFGR_XBARxSEL_MASK;
1265
1266 return sel;
1267 }
1268
clk_flexgen_gate_enable(struct stm32_clk_priv * priv,int idx)1269 static int clk_flexgen_gate_enable(struct stm32_clk_priv *priv, int idx)
1270 {
1271 const struct clk_stm32 *clk = _clk_get(priv, idx);
1272 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
1273 uintptr_t rcc_base = priv->base;
1274 uint8_t channel = cfg->id;
1275
1276 mmio_setbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel),
1277 RCC_FINDIVxCFGR_FINDIVxEN);
1278
1279 return 0;
1280 }
1281
clk_flexgen_gate_disable(struct stm32_clk_priv * priv,int id)1282 static void clk_flexgen_gate_disable(struct stm32_clk_priv *priv, int id)
1283 {
1284 const struct clk_stm32 *clk = _clk_get(priv, id);
1285 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
1286 uintptr_t rcc_base = priv->base;
1287 uint8_t channel = cfg->id;
1288
1289 mmio_clrbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel),
1290 RCC_FINDIVxCFGR_FINDIVxEN);
1291 }
1292
clk_flexgen_gate_is_enabled(struct stm32_clk_priv * priv,int id)1293 static bool clk_flexgen_gate_is_enabled(struct stm32_clk_priv *priv, int id)
1294 {
1295 const struct clk_stm32 *clk = _clk_get(priv, id);
1296 struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
1297 uintptr_t rcc_base = priv->base;
1298 uint8_t channel = cfg->id;
1299
1300 return !!(mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) &
1301 RCC_FINDIVxCFGR_FINDIVxEN);
1302 }
1303
1304 static const struct stm32_clk_ops clk_stm32_flexgen_ops = {
1305 .recalc_rate = clk_flexgen_recalc,
1306 .get_parent = clk_flexgen_get_parent,
1307 .enable = clk_flexgen_gate_enable,
1308 .disable = clk_flexgen_gate_disable,
1309 .is_enabled = clk_flexgen_gate_is_enabled,
1310 };
1311
1312 #define FLEXGEN(idx, _idx, _flags, _id)[idx] = {\
1313 .binding = _idx,\
1314 .parent = MUX(MUX_XBARSEL),\
1315 .flags = (_flags),\
1316 .clock_cfg = &(struct stm32_clk_flexgen_cfg) {\
1317 .id = _id,\
1318 },\
1319 .ops = STM32_FLEXGEN_OPS,\
1320 }
1321
1322 #define RCC_0_MHZ UL(0)
1323 #define RCC_4_MHZ UL(4000000)
1324 #define RCC_16_MHZ UL(16000000)
1325
1326 #ifdef IMAGE_BL2
1327 #if !STM32MP21
clk_stm32_osc_msi_set_rate(struct stm32_clk_priv * priv,int id,unsigned long rate,unsigned long prate)1328 static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
1329 unsigned long prate)
1330 {
1331 uintptr_t address = priv->base + RCC_BDCR;
1332 uint32_t mask = RCC_BDCR_MSIFREQSEL;
1333 int ret = -1;
1334
1335 switch (rate) {
1336 case RCC_4_MHZ:
1337 mmio_clrbits_32(address, mask);
1338 ret = 0;
1339 break;
1340
1341 case RCC_16_MHZ:
1342 mmio_setbits_32(address, mask);
1343 ret = 0;
1344 break;
1345
1346 default:
1347 break;
1348 }
1349
1350 return ret;
1351 }
1352 #endif /* !STM32MP21 */
1353 #endif /* IMAGE_BL2 */
1354
clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv * priv,int id __unused,unsigned long prate __unused)1355 static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,
1356 int id __unused,
1357 unsigned long prate __unused)
1358 {
1359 #if STM32MP21
1360 return RCC_16_MHZ;
1361 #else /* STM32MP21 */
1362 uintptr_t address = priv->base + RCC_BDCR;
1363
1364 if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) {
1365 return RCC_4_MHZ;
1366 } else {
1367 return RCC_16_MHZ;
1368 }
1369 #endif /* STM32MP21 */
1370 }
1371
1372 static const struct stm32_clk_ops clk_stm32_osc_msi_ops = {
1373 .recalc_rate = clk_stm32_osc_msi_recalc_rate,
1374 .is_enabled = clk_stm32_osc_gate_is_enabled,
1375 .enable = clk_stm32_osc_gate_enable,
1376 .disable = clk_stm32_osc_gate_disable,
1377 .init = clk_stm32_osc_init,
1378 };
1379
1380 #define CLK_OSC(idx, _idx, _parent, _osc_id) \
1381 [(idx)] = (struct clk_stm32){ \
1382 .binding = (_idx),\
1383 .parent = (_parent),\
1384 .flags = CLK_IS_CRITICAL,\
1385 .clock_cfg = &(struct stm32_osc_cfg){\
1386 .osc_id = (_osc_id),\
1387 },\
1388 .ops = STM32_OSC_OPS,\
1389 }
1390
1391 #define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \
1392 [(idx)] = (struct clk_stm32){ \
1393 .binding = (_idx),\
1394 .parent = (_parent),\
1395 .flags = CLK_IS_CRITICAL,\
1396 .clock_cfg = &(struct stm32_osc_cfg){\
1397 .osc_id = (_osc_id),\
1398 },\
1399 .ops = STM32_OSC_NOGATE_OPS,\
1400 }
1401
1402 #define CLK_OSC_MSI(idx, _idx, _parent, _osc_id) \
1403 [(idx)] = (struct clk_stm32){ \
1404 .binding = (_idx),\
1405 .parent = (_parent),\
1406 .flags = CLK_IS_CRITICAL,\
1407 .clock_cfg = &(struct stm32_osc_cfg){\
1408 .osc_id = (_osc_id),\
1409 },\
1410 .ops = STM32_OSC_MSI_OPS,\
1411 }
1412
1413 static const struct stm32_clk_ops clk_stm32_rtc_ops = {
1414 .enable = clk_stm32_gate_enable,
1415 .disable = clk_stm32_gate_disable,
1416 .is_enabled = clk_stm32_gate_is_enabled,
1417 };
1418
1419 #define CLK_RTC(idx, _binding, _parent, _flags, _gate_id)[idx] = {\
1420 .binding = (_binding),\
1421 .parent = (_parent),\
1422 .flags = (_flags),\
1423 .clock_cfg = &(struct clk_stm32_gate_cfg) {\
1424 .id = (_gate_id),\
1425 },\
1426 .ops = STM32_RTC_OPS,\
1427 }
1428
1429 enum {
1430 STM32_PLL_OPS = STM32_LAST_OPS,
1431 STM32_PLL1_OPS,
1432 STM32_FLEXGEN_OPS,
1433 STM32_OSC_OPS,
1434 STM32_OSC_NOGATE_OPS,
1435 STM32_OSC_MSI_OPS,
1436 STM32_RTC_OPS,
1437
1438 MP2_LAST_OPS
1439 };
1440
1441 static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = {
1442 [NO_OPS] = NULL,
1443 [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
1444 [GATE_OPS] = &clk_gate_ops,
1445 [STM32_MUX_OPS] = &clk_mux_ops,
1446 [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops,
1447 [STM32_GATE_OPS] = &clk_stm32_gate_ops,
1448 [STM32_TIMER_OPS] = &clk_timer_ops,
1449 [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops,
1450 [STM32_OSC_OPS] = &clk_stm32_osc_ops,
1451 [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops,
1452
1453 [STM32_PLL_OPS] = &clk_stm32_pll_ops,
1454 [STM32_PLL1_OPS] = &clk_stm32_pll1_ops,
1455 [STM32_FLEXGEN_OPS] = &clk_stm32_flexgen_ops,
1456 [STM32_OSC_MSI_OPS] = &clk_stm32_osc_msi_ops,
1457 [STM32_RTC_OPS] = &clk_stm32_rtc_ops
1458 };
1459
1460 static const struct clk_stm32 stm32mp2_clk[CK_LAST] = {
1461 CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ),
1462
1463 /* ROOT CLOCKS */
1464 CLK_OSC(_CK_HSE, HSE_CK, CLK_IS_ROOT, OSC_HSE),
1465 CLK_OSC(_CK_LSE, LSE_CK, CLK_IS_ROOT, OSC_LSE),
1466 CLK_OSC(_CK_HSI, HSI_CK, CLK_IS_ROOT, OSC_HSI),
1467 CLK_OSC(_CK_LSI, LSI_CK, CLK_IS_ROOT, OSC_LSI),
1468 CLK_OSC_MSI(_CK_MSI, MSI_CK, CLK_IS_ROOT, OSC_MSI),
1469
1470 CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN),
1471 CLK_OSC_FIXED(_SPDIFSYMB, _NO_ID, CLK_IS_ROOT, OSC_SPDIFSYMB),
1472
1473 STM32_DIV(_CK_HSE_RTC, _NO_ID, _CK_HSE, 0, DIV_RTC),
1474
1475 CLK_RTC(_CK_RTCCK, RTC_CK, MUX(MUX_RTC), 0, GATE_RTCCK),
1476
1477 CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
1478
1479 CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
1480 #if !STM32MP21
1481 CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
1482 #endif /* !STM32MP21 */
1483 CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
1484 CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
1485 CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
1486 CLK_PLL(_CK_PLL7, PLL7_CK, MUX(MUX_MUXSEL3), _PLL7, 0),
1487 CLK_PLL(_CK_PLL8, PLL8_CK, MUX(MUX_MUXSEL4), _PLL8, 0),
1488
1489 FLEXGEN(_CK_ICN_HS_MCU, CK_ICN_HS_MCU, CLK_IS_CRITICAL, 0),
1490 FLEXGEN(_CK_ICN_SDMMC, CK_ICN_SDMMC, CLK_IS_CRITICAL, 1),
1491 FLEXGEN(_CK_ICN_DDR, CK_ICN_DDR, CLK_IS_CRITICAL, 2),
1492 FLEXGEN(_CK_ICN_HSL, CK_ICN_HSL, CLK_IS_CRITICAL, 4),
1493 FLEXGEN(_CK_ICN_NIC, CK_ICN_NIC, CLK_IS_CRITICAL, 5),
1494
1495 STM32_DIV(_CK_ICN_LS_MCU, CK_ICN_LS_MCU, _CK_ICN_HS_MCU, 0, DIV_LSMCU),
1496
1497 FLEXGEN(_CK_FLEXGEN_07, CK_FLEXGEN_07, 0, 7),
1498 FLEXGEN(_CK_FLEXGEN_08, CK_FLEXGEN_08, 0, 8),
1499 FLEXGEN(_CK_FLEXGEN_09, CK_FLEXGEN_09, 0, 9),
1500 FLEXGEN(_CK_FLEXGEN_10, CK_FLEXGEN_10, 0, 10),
1501 FLEXGEN(_CK_FLEXGEN_11, CK_FLEXGEN_11, 0, 11),
1502 FLEXGEN(_CK_FLEXGEN_12, CK_FLEXGEN_12, 0, 12),
1503 FLEXGEN(_CK_FLEXGEN_13, CK_FLEXGEN_13, 0, 13),
1504 FLEXGEN(_CK_FLEXGEN_14, CK_FLEXGEN_14, 0, 14),
1505 FLEXGEN(_CK_FLEXGEN_15, CK_FLEXGEN_15, 0, 15),
1506 FLEXGEN(_CK_FLEXGEN_16, CK_FLEXGEN_16, 0, 16),
1507 FLEXGEN(_CK_FLEXGEN_17, CK_FLEXGEN_17, 0, 17),
1508 FLEXGEN(_CK_FLEXGEN_18, CK_FLEXGEN_18, 0, 18),
1509 FLEXGEN(_CK_FLEXGEN_19, CK_FLEXGEN_19, 0, 19),
1510 FLEXGEN(_CK_FLEXGEN_20, CK_FLEXGEN_20, 0, 20),
1511 FLEXGEN(_CK_FLEXGEN_21, CK_FLEXGEN_21, 0, 21),
1512 FLEXGEN(_CK_FLEXGEN_22, CK_FLEXGEN_22, 0, 22),
1513 FLEXGEN(_CK_FLEXGEN_23, CK_FLEXGEN_23, 0, 23),
1514 FLEXGEN(_CK_FLEXGEN_24, CK_FLEXGEN_24, 0, 24),
1515 FLEXGEN(_CK_FLEXGEN_25, CK_FLEXGEN_25, 0, 25),
1516 FLEXGEN(_CK_FLEXGEN_26, CK_FLEXGEN_26, 0, 26),
1517 FLEXGEN(_CK_FLEXGEN_27, CK_FLEXGEN_27, 0, 27),
1518 FLEXGEN(_CK_FLEXGEN_28, CK_FLEXGEN_28, 0, 28),
1519 FLEXGEN(_CK_FLEXGEN_29, CK_FLEXGEN_29, 0, 29),
1520 FLEXGEN(_CK_FLEXGEN_30, CK_FLEXGEN_30, 0, 30),
1521 FLEXGEN(_CK_FLEXGEN_31, CK_FLEXGEN_31, 0, 31),
1522 FLEXGEN(_CK_FLEXGEN_32, CK_FLEXGEN_32, 0, 32),
1523 FLEXGEN(_CK_FLEXGEN_33, CK_FLEXGEN_33, 0, 33),
1524 FLEXGEN(_CK_FLEXGEN_34, CK_FLEXGEN_34, 0, 34),
1525 FLEXGEN(_CK_FLEXGEN_35, CK_FLEXGEN_35, 0, 35),
1526 FLEXGEN(_CK_FLEXGEN_36, CK_FLEXGEN_36, 0, 36),
1527 FLEXGEN(_CK_FLEXGEN_37, CK_FLEXGEN_37, 0, 37),
1528 FLEXGEN(_CK_FLEXGEN_38, CK_FLEXGEN_38, 0, 38),
1529 FLEXGEN(_CK_FLEXGEN_39, CK_FLEXGEN_39, 0, 39),
1530 FLEXGEN(_CK_FLEXGEN_40, CK_FLEXGEN_40, 0, 40),
1531 FLEXGEN(_CK_FLEXGEN_41, CK_FLEXGEN_41, 0, 41),
1532 FLEXGEN(_CK_FLEXGEN_42, CK_FLEXGEN_42, 0, 42),
1533 FLEXGEN(_CK_FLEXGEN_43, CK_FLEXGEN_43, 0, 43),
1534 FLEXGEN(_CK_FLEXGEN_44, CK_FLEXGEN_44, 0, 44),
1535 FLEXGEN(_CK_FLEXGEN_45, CK_FLEXGEN_45, 0, 45),
1536 FLEXGEN(_CK_FLEXGEN_46, CK_FLEXGEN_46, 0, 46),
1537 FLEXGEN(_CK_FLEXGEN_47, CK_FLEXGEN_47, 0, 47),
1538 FLEXGEN(_CK_FLEXGEN_48, CK_FLEXGEN_48, 0, 48),
1539 FLEXGEN(_CK_FLEXGEN_49, CK_FLEXGEN_49, 0, 49),
1540 FLEXGEN(_CK_FLEXGEN_50, CK_FLEXGEN_50, 0, 50),
1541 FLEXGEN(_CK_FLEXGEN_51, CK_FLEXGEN_51, 0, 51),
1542 FLEXGEN(_CK_FLEXGEN_52, CK_FLEXGEN_52, 0, 52),
1543 FLEXGEN(_CK_FLEXGEN_53, CK_FLEXGEN_53, 0, 53),
1544 FLEXGEN(_CK_FLEXGEN_54, CK_FLEXGEN_54, 0, 54),
1545 FLEXGEN(_CK_FLEXGEN_55, CK_FLEXGEN_55, 0, 55),
1546 FLEXGEN(_CK_FLEXGEN_56, CK_FLEXGEN_56, 0, 56),
1547 FLEXGEN(_CK_FLEXGEN_57, CK_FLEXGEN_57, 0, 57),
1548 FLEXGEN(_CK_FLEXGEN_58, CK_FLEXGEN_58, 0, 58),
1549 FLEXGEN(_CK_FLEXGEN_59, CK_FLEXGEN_59, 0, 59),
1550 FLEXGEN(_CK_FLEXGEN_60, CK_FLEXGEN_60, 0, 60),
1551 FLEXGEN(_CK_FLEXGEN_61, CK_FLEXGEN_61, 0, 61),
1552 FLEXGEN(_CK_FLEXGEN_62, CK_FLEXGEN_62, 0, 62),
1553 FLEXGEN(_CK_FLEXGEN_63, CK_FLEXGEN_63, 0, 63),
1554
1555 STM32_DIV(_CK_ICN_APB1, CK_ICN_APB1, _CK_ICN_LS_MCU, 0, DIV_APB1),
1556 STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2),
1557 STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3),
1558 STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4),
1559 #if STM32MP21
1560 STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5),
1561 #endif /* STM32MP21 */
1562 STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG),
1563
1564 /* KERNEL CLOCK */
1565 STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM),
1566 STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM),
1567 STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1),
1568 #if !STM32MP21
1569 STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2),
1570 #endif /* !STM32MP21 */
1571
1572 STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC),
1573 STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1),
1574 STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC),
1575 #if !STM32MP21
1576 STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM),
1577 #endif /* !STM32MP21 */
1578 STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM),
1579 #if STM32MP21
1580 STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1),
1581 STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2),
1582 STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1),
1583 STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2),
1584 #else /* STM32MP21 */
1585 STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH),
1586 STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG),
1587 #endif /* STM32MP21 */
1588 STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1),
1589 STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2),
1590 STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES),
1591 STM32_GATE(_CK_PKA, CK_BUS_PKA, _CK_ICN_LS_MCU, 0, GATE_PKA),
1592
1593 STM32_GATE(_CK_GPIOA, CK_BUS_GPIOA, _CK_ICN_LS_MCU, 0, GATE_GPIOA),
1594 STM32_GATE(_CK_GPIOB, CK_BUS_GPIOB, _CK_ICN_LS_MCU, 0, GATE_GPIOB),
1595 STM32_GATE(_CK_GPIOC, CK_BUS_GPIOC, _CK_ICN_LS_MCU, 0, GATE_GPIOC),
1596 STM32_GATE(_CK_GPIOD, CK_BUS_GPIOD, _CK_ICN_LS_MCU, 0, GATE_GPIOD),
1597 STM32_GATE(_CK_GPIOE, CK_BUS_GPIOE, _CK_ICN_LS_MCU, 0, GATE_GPIOE),
1598 STM32_GATE(_CK_GPIOF, CK_BUS_GPIOF, _CK_ICN_LS_MCU, 0, GATE_GPIOF),
1599 STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG),
1600 STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH),
1601 STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI),
1602 #if !STM32MP21
1603 STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ),
1604 STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK),
1605 #endif /* !STM32MP21 */
1606 STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ),
1607 STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, CLK_IS_CRITICAL, GATE_RTC),
1608
1609 STM32_GATE(_CK_BUS_RISAF4, CK_BUS_RISAF4, _CK_ICN_LS_MCU, CLK_IS_CRITICAL, GATE_DDRCP),
1610 STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, CLK_IS_CRITICAL, GATE_DDRCP),
1611
1612 /* WARNING 2 CLOCKS FOR ONE GATE */
1613 #if STM32MP21
1614 STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI),
1615 STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI),
1616 #else /* STM32MP21 */
1617 STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI),
1618 STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI),
1619 #endif /* STM32MP21 */
1620
1621 #if !STM32MP21
1622 STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR),
1623 #endif /* !STM32MP21 */
1624
1625 STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC),
1626 STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1),
1627 STM32_GATE(_CK_IWDG2, CK_BUS_IWDG2, _CK_ICN_APB3, 0, GATE_IWDG2),
1628
1629 STM32_GATE(_CK_DDRCAPB, CK_BUS_DDRC, _CK_ICN_APB4, 0, GATE_DDRCAPB),
1630 STM32_GATE(_CK_DDR, CK_BUS_DDRCFG, _CK_ICN_APB4, 0, GATE_DDR),
1631
1632 STM32_GATE(_CK_SYSDBG, CK_SYSDBG, _CK_ICN_APBDBG, 0, GATE_DBG),
1633
1634 STM32_GATE(_CK_USART2, CK_KER_USART2, _CK_FLEXGEN_08, 0, GATE_USART2),
1635 STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4),
1636 STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3),
1637 STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5),
1638 #if STM32MP21
1639 STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1),
1640 STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2),
1641 STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1),
1642 STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6),
1643 STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7),
1644 STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3),
1645 #else /* STM32MP21 */
1646 STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1),
1647 STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2),
1648 #if STM32MP25
1649 STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3),
1650 STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5),
1651 STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4),
1652 STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6),
1653 #endif /* STM32MP25 */
1654 STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7),
1655 STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1),
1656 STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6),
1657 STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7),
1658 #if STM32MP25
1659 STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8),
1660 STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9),
1661 #endif /* STM32MP25 */
1662 #endif /* STM32MP21 */
1663 STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN),
1664 #if !STM32MP21
1665 STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY),
1666 STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC),
1667 STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8),
1668 #endif /* !STM32MP21 */
1669 STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1),
1670 #if !STM32MP21
1671 STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2),
1672 #endif /* !STM32MP21 */
1673 STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC),
1674 STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1),
1675 STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2),
1676 STM32_GATE(_CK_USB2PHY1, CK_KER_USB2PHY1, _CK_FLEXGEN_57, 0, GATE_USB2PHY1),
1677 STM32_GATE(_CK_USB2PHY2, CK_KER_USB2PHY2, _CK_FLEXGEN_58, 0, GATE_USB2PHY2),
1678 };
1679
1680 enum clksrc_id {
1681 CLKSRC_CA35SS,
1682 CLKSRC_PLL1,
1683 CLKSRC_PLL2,
1684 #if !STM32MP21
1685 CLKSRC_PLL3,
1686 #endif /* !STM32MP21 */
1687 CLKSRC_PLL4,
1688 CLKSRC_PLL5,
1689 CLKSRC_PLL6,
1690 CLKSRC_PLL7,
1691 CLKSRC_PLL8,
1692 CLKSRC_XBAR_CHANNEL0,
1693 CLKSRC_XBAR_CHANNEL1,
1694 CLKSRC_XBAR_CHANNEL2,
1695 CLKSRC_XBAR_CHANNEL3,
1696 CLKSRC_XBAR_CHANNEL4,
1697 CLKSRC_XBAR_CHANNEL5,
1698 CLKSRC_XBAR_CHANNEL6,
1699 CLKSRC_XBAR_CHANNEL7,
1700 CLKSRC_XBAR_CHANNEL8,
1701 CLKSRC_XBAR_CHANNEL9,
1702 CLKSRC_XBAR_CHANNEL10,
1703 CLKSRC_XBAR_CHANNEL11,
1704 CLKSRC_XBAR_CHANNEL12,
1705 CLKSRC_XBAR_CHANNEL13,
1706 CLKSRC_XBAR_CHANNEL14,
1707 CLKSRC_XBAR_CHANNEL15,
1708 CLKSRC_XBAR_CHANNEL16,
1709 CLKSRC_XBAR_CHANNEL17,
1710 CLKSRC_XBAR_CHANNEL18,
1711 CLKSRC_XBAR_CHANNEL19,
1712 CLKSRC_XBAR_CHANNEL20,
1713 CLKSRC_XBAR_CHANNEL21,
1714 CLKSRC_XBAR_CHANNEL22,
1715 CLKSRC_XBAR_CHANNEL23,
1716 CLKSRC_XBAR_CHANNEL24,
1717 CLKSRC_XBAR_CHANNEL25,
1718 CLKSRC_XBAR_CHANNEL26,
1719 CLKSRC_XBAR_CHANNEL27,
1720 CLKSRC_XBAR_CHANNEL28,
1721 CLKSRC_XBAR_CHANNEL29,
1722 CLKSRC_XBAR_CHANNEL30,
1723 CLKSRC_XBAR_CHANNEL31,
1724 CLKSRC_XBAR_CHANNEL32,
1725 CLKSRC_XBAR_CHANNEL33,
1726 CLKSRC_XBAR_CHANNEL34,
1727 CLKSRC_XBAR_CHANNEL35,
1728 CLKSRC_XBAR_CHANNEL36,
1729 CLKSRC_XBAR_CHANNEL37,
1730 CLKSRC_XBAR_CHANNEL38,
1731 CLKSRC_XBAR_CHANNEL39,
1732 CLKSRC_XBAR_CHANNEL40,
1733 CLKSRC_XBAR_CHANNEL41,
1734 CLKSRC_XBAR_CHANNEL42,
1735 CLKSRC_XBAR_CHANNEL43,
1736 CLKSRC_XBAR_CHANNEL44,
1737 CLKSRC_XBAR_CHANNEL45,
1738 CLKSRC_XBAR_CHANNEL46,
1739 CLKSRC_XBAR_CHANNEL47,
1740 CLKSRC_XBAR_CHANNEL48,
1741 CLKSRC_XBAR_CHANNEL49,
1742 CLKSRC_XBAR_CHANNEL50,
1743 CLKSRC_XBAR_CHANNEL51,
1744 CLKSRC_XBAR_CHANNEL52,
1745 CLKSRC_XBAR_CHANNEL53,
1746 CLKSRC_XBAR_CHANNEL54,
1747 CLKSRC_XBAR_CHANNEL55,
1748 CLKSRC_XBAR_CHANNEL56,
1749 CLKSRC_XBAR_CHANNEL57,
1750 CLKSRC_XBAR_CHANNEL58,
1751 CLKSRC_XBAR_CHANNEL59,
1752 CLKSRC_XBAR_CHANNEL60,
1753 CLKSRC_XBAR_CHANNEL61,
1754 CLKSRC_XBAR_CHANNEL62,
1755 CLKSRC_XBAR_CHANNEL63,
1756 CLKSRC_RTC,
1757 CLKSRC_MCO1,
1758 CLKSRC_MCO2,
1759 CLKSRC_NB
1760 };
1761
stm32mp2_a35_ss_on_hsi(void)1762 static void stm32mp2_a35_ss_on_hsi(void)
1763 {
1764 uintptr_t a35_ss_address = A35SSC_BASE;
1765 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ;
1766 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;
1767 uint32_t chgclkreq;
1768 uint64_t timeout;
1769
1770 chgclkreq = mmio_read_32(chgclkreq_reg);
1771 if ((chgclkreq & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) == A35_SS_CHGCLKREQ_ARM_CHGCLKACK) {
1772 /* Nothing to do, clock source is already set on bypass clock */
1773 return;
1774 }
1775
1776 /* for clkext2f frequency at 400MHZ, default flexgen63 config, divider by 2 is required */
1777 if ((chgclkreq & A35_SS_CHGCLKREQ_ARM_DIVSEL) == A35_SS_CHGCLKREQ_ARM_DIVSEL) {
1778 mmio_clrbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_DIVSEL);
1779 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1780 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_DIVSELACK) ==
1781 A35_SS_CHGCLKREQ_ARM_DIVSELACK) {
1782 if (timeout_elapsed(timeout)) {
1783 EARLY_ERROR("Cannot set div on A35 bypass clock\n");
1784 panic();
1785 }
1786 }
1787 }
1788
1789 mmio_setbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ);
1790
1791 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1792 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) !=
1793 A35_SS_CHGCLKREQ_ARM_CHGCLKACK) {
1794 if (timeout_elapsed(timeout)) {
1795 EARLY_ERROR("Cannot switch A35 to bypass clock\n");
1796 panic();
1797 }
1798 }
1799
1800 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF);
1801 }
1802
1803 #ifdef IMAGE_BL2
stm32mp2_clk_muxsel_on_hsi(struct stm32_clk_priv * priv)1804 static void stm32mp2_clk_muxsel_on_hsi(struct stm32_clk_priv *priv)
1805 {
1806 mmio_clrbits_32(priv->base + RCC_MUXSELCFGR,
1807 RCC_MUXSELCFGR_MUXSEL0_MASK |
1808 RCC_MUXSELCFGR_MUXSEL1_MASK |
1809 RCC_MUXSELCFGR_MUXSEL2_MASK |
1810 RCC_MUXSELCFGR_MUXSEL3_MASK |
1811 RCC_MUXSELCFGR_MUXSEL4_MASK |
1812 RCC_MUXSELCFGR_MUXSEL5_MASK |
1813 RCC_MUXSELCFGR_MUXSEL6_MASK |
1814 RCC_MUXSELCFGR_MUXSEL7_MASK);
1815 }
1816
stm32mp2_clk_xbar_on_hsi(struct stm32_clk_priv * priv)1817 static void stm32mp2_clk_xbar_on_hsi(struct stm32_clk_priv *priv)
1818 {
1819 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR;
1820 uint32_t i;
1821
1822 for (i = 0; i < XBAR_CHANNEL_NB; i++) {
1823 mmio_clrsetbits_32(xbar0cfgr + (0x4 * i),
1824 RCC_XBAR0CFGR_XBAR0SEL_MASK,
1825 XBAR_SRC_HSI);
1826 }
1827 }
1828
stm32mp2_a35_pll1_start(void)1829 static int stm32mp2_a35_pll1_start(void)
1830 {
1831 uintptr_t a35_ss_address = A35SSC_BASE;
1832 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;
1833 uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ;
1834 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1835
1836 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD);
1837
1838 /* Wait PLL lock */
1839 while ((mmio_read_32(pll_enable_reg) & A35_SS_PLL_ENABLE_LOCKP) == 0U) {
1840 if (timeout_elapsed(timeout)) {
1841 EARLY_ERROR("PLL1 start failed @ 0x%lx: 0x%x\n",
1842 pll_enable_reg, mmio_read_32(pll_enable_reg));
1843 return -ETIMEDOUT;
1844 }
1845 }
1846
1847 /* De-assert reset on PLL output clock path */
1848 mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF);
1849
1850 /* Switch CPU clock to PLL clock */
1851 mmio_clrbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ);
1852
1853 /* Wait for clock change acknowledge */
1854 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1855 while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 0U) {
1856 if (timeout_elapsed(timeout)) {
1857 EARLY_ERROR("CA35SS switch to PLL1 failed @ 0x%lx: 0x%x\n",
1858 chgclkreq_reg, mmio_read_32(chgclkreq_reg));
1859 return -ETIMEDOUT;
1860 }
1861 }
1862
1863 return 0;
1864 }
1865
stm32mp2_a35_pll1_config(uint32_t fbdiv,uint32_t refdiv,uint32_t postdiv1,uint32_t postdiv2)1866 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, uint32_t postdiv1,
1867 uint32_t postdiv2)
1868 {
1869 uintptr_t a35_ss_address = A35SSC_BASE;
1870 uintptr_t pll_freq1_reg = a35_ss_address + A35_SS_PLL_FREQ1;
1871 uintptr_t pll_freq2_reg = a35_ss_address + A35_SS_PLL_FREQ2;
1872
1873 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_REFDIV_MASK,
1874 (refdiv << A35_SS_PLL_FREQ1_REFDIV_SHIFT) &
1875 A35_SS_PLL_FREQ1_REFDIV_MASK);
1876
1877 mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_FBDIV_MASK,
1878 (fbdiv << A35_SS_PLL_FREQ1_FBDIV_SHIFT) &
1879 A35_SS_PLL_FREQ1_FBDIV_MASK);
1880
1881 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV1_MASK,
1882 (postdiv1 << A35_SS_PLL_FREQ2_POSTDIV1_SHIFT) &
1883 A35_SS_PLL_FREQ2_POSTDIV1_MASK);
1884
1885 mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV2_MASK,
1886 (postdiv2 << A35_SS_PLL_FREQ2_POSTDIV2_SHIFT) &
1887 A35_SS_PLL_FREQ2_POSTDIV2_MASK);
1888 }
1889
clk_stm32_pll_config_output(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,uint32_t * pllcfg,uint32_t fracv)1890 static int clk_stm32_pll_config_output(struct stm32_clk_priv *priv,
1891 const struct stm32_clk_pll *pll,
1892 uint32_t *pllcfg,
1893 uint32_t fracv)
1894 {
1895 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1896 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
1897 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
1898 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
1899 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
1900 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
1901 unsigned long refclk;
1902
1903 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);
1904
1905 if (fracv == 0U) {
1906 /* PLL in integer mode */
1907
1908 /*
1909 * No need to check max clock, as oscillator reference clocks
1910 * will always be less than 1.2GHz
1911 */
1912 if (refclk < PLL_REFCLK_MIN) {
1913 panic();
1914 }
1915
1916 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK);
1917 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1918 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
1919 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1920 mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
1921 } else {
1922 /* PLL in frac mode */
1923
1924 /*
1925 * No need to check max clock, as oscillator reference clocks
1926 * will always be less than 1.2GHz
1927 */
1928 if (refclk < PLL_FRAC_REFCLK_MIN) {
1929 panic();
1930 }
1931
1932 mmio_clrsetbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK,
1933 fracv & RCC_PLLxCFGR3_FRACIN_MASK);
1934 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1935 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1936 }
1937
1938 assert(pllcfg[REFDIV] != 0U);
1939
1940 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK,
1941 (pllcfg[FBDIV] << RCC_PLLxCFGR2_FBDIV_SHIFT) &
1942 RCC_PLLxCFGR2_FBDIV_MASK);
1943 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK,
1944 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK);
1945 mmio_clrsetbits_32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK,
1946 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK);
1947 mmio_clrsetbits_32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK,
1948 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK);
1949
1950 if ((pllcfg[POSTDIV1] == 0U) || (pllcfg[POSTDIV2] == 0U)) {
1951 /* Bypass mode */
1952 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
1953 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
1954 } else {
1955 mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
1956 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
1957 }
1958
1959 return 0;
1960 }
1961
clk_stm32_pll_config_csg(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll,uint32_t * csg)1962 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv,
1963 const struct stm32_clk_pll *pll,
1964 uint32_t *csg)
1965 {
1966 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1967 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
1968 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
1969 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5;
1970
1971
1972 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK,
1973 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK);
1974 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK,
1975 (csg[SPREAD] << RCC_PLLxCFGR5_SPREAD_SHIFT) &
1976 RCC_PLLxCFGR5_SPREAD_MASK);
1977
1978 if (csg[DOWNSPREAD] != 0) {
1979 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
1980 } else {
1981 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
1982 }
1983
1984 mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1985
1986 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
1987 udelay(1);
1988
1989 mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1990 mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
1991 }
1992
1993 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data);
1994
clk_stm32_pll_get_pdata(int pll_idx)1995 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx)
1996 {
1997 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1998 struct stm32_clk_platdata *pdata = priv->pdata;
1999
2000 return &pdata->pll[pll_idx];
2001 }
2002
_clk_stm32_pll1_init(struct stm32_clk_priv * priv,int pll_idx,struct stm32_pll_dt_cfg * pll_conf)2003 static int _clk_stm32_pll1_init(struct stm32_clk_priv *priv, int pll_idx,
2004 struct stm32_pll_dt_cfg *pll_conf)
2005 {
2006 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);
2007 unsigned long refclk;
2008 int ret = 0;
2009
2010 stm32mp2_a35_ss_on_hsi();
2011
2012 ret = stm32_clk_configure_mux(priv, pll_conf->src);
2013 if (ret != 0) {
2014 panic();
2015 }
2016
2017 refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);
2018
2019 /*
2020 * No need to check max clock, as oscillator reference clocks will
2021 * always be less than 1.2 GHz
2022 */
2023 if (refclk < PLL_REFCLK_MIN) {
2024 EARLY_ERROR("%s: %d\n", __func__, __LINE__);
2025 panic();
2026 }
2027
2028 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], pll_conf->cfg[REFDIV],
2029 pll_conf->cfg[POSTDIV1], pll_conf->cfg[POSTDIV2]);
2030
2031 ret = stm32mp2_a35_pll1_start();
2032 if (ret != 0) {
2033 panic();
2034 }
2035
2036 return 0;
2037 }
2038
clk_stm32_pll_wait_mux_ready(struct stm32_clk_priv * priv,const struct stm32_clk_pll * pll)2039 static int clk_stm32_pll_wait_mux_ready(struct stm32_clk_priv *priv,
2040 const struct stm32_clk_pll *pll)
2041 {
2042 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
2043 uint64_t timeout = timeout_init_us(CLKSRC_TIMEOUT);
2044
2045 while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_CKREFST) !=
2046 RCC_PLLxCFGR1_CKREFST) {
2047 if (timeout_elapsed(timeout)) {
2048 EARLY_ERROR("PLL%d ref clock not started\n", pll->clk_id - _CK_PLL1 + 1);
2049 return -ETIMEDOUT;
2050 }
2051 }
2052
2053 return 0;
2054 }
2055
_clk_stm32_pll_init(struct stm32_clk_priv * priv,int pll_idx,struct stm32_pll_dt_cfg * pll_conf)2056 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx,
2057 struct stm32_pll_dt_cfg *pll_conf)
2058 {
2059 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);
2060 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
2061 bool spread_spectrum = false;
2062 int ret = 0;
2063
2064 _clk_stm32_pll_disable(priv, pll);
2065
2066 ret = stm32_clk_configure_mux(priv, pll_conf->src);
2067 if (ret != 0) {
2068 panic();
2069 }
2070
2071 ret = clk_stm32_pll_wait_mux_ready(priv, pll);
2072 if (ret != 0) {
2073 panic();
2074 }
2075
2076 ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac);
2077 if (ret != 0) {
2078 panic();
2079 }
2080
2081 if (pll_conf->csg_enabled) {
2082 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);
2083 spread_spectrum = true;
2084 }
2085
2086 _clk_stm32_pll_enable(priv, pll);
2087
2088 if (spread_spectrum) {
2089 mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
2090 }
2091
2092 return 0;
2093 }
2094
clk_stm32_pll_init(struct stm32_clk_priv * priv,int pll_idx)2095 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx)
2096 {
2097 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx);
2098
2099 if (pll_conf->enabled) {
2100 if (pll_idx == _PLL1) {
2101 return _clk_stm32_pll1_init(priv, pll_idx, pll_conf);
2102 } else {
2103 return _clk_stm32_pll_init(priv, pll_idx, pll_conf);
2104 }
2105 }
2106
2107 return 0;
2108 }
2109
stm32mp2_clk_pll_configure(struct stm32_clk_priv * priv)2110 static int stm32mp2_clk_pll_configure(struct stm32_clk_priv *priv)
2111 {
2112 enum pll_id i;
2113 int err;
2114
2115 for (i = _PLL1; i < _PLL_NB; i++) {
2116 #if STM32MP21
2117 if (i == _PLL3) {
2118 continue;
2119 }
2120 #endif
2121 err = clk_stm32_pll_init(priv, i);
2122 if (err) {
2123 return err;
2124 }
2125 }
2126
2127 return 0;
2128 }
2129
wait_predivsr(uint16_t channel)2130 static int wait_predivsr(uint16_t channel)
2131 {
2132 struct stm32_clk_priv *priv = clk_stm32_get_priv();
2133 uintptr_t rcc_base = priv->base;
2134 uintptr_t previvsr;
2135 uint32_t channel_bit;
2136 uint64_t timeout;
2137
2138 if (channel < __WORD_BIT) {
2139 previvsr = rcc_base + RCC_PREDIVSR1;
2140 channel_bit = BIT(channel);
2141 } else {
2142 previvsr = rcc_base + RCC_PREDIVSR2;
2143 channel_bit = BIT(channel - __WORD_BIT);
2144 }
2145
2146 timeout = timeout_init_us(CLKDIV_TIMEOUT);
2147 while ((mmio_read_32(previvsr) & channel_bit) != 0U) {
2148 if (timeout_elapsed(timeout)) {
2149 EARLY_ERROR("Pre divider status: %x\n",
2150 mmio_read_32(previvsr));
2151 return -ETIMEDOUT;
2152 }
2153 }
2154
2155 return 0;
2156 }
2157
wait_findivsr(uint16_t channel)2158 static int wait_findivsr(uint16_t channel)
2159 {
2160 struct stm32_clk_priv *priv = clk_stm32_get_priv();
2161 uintptr_t rcc_base = priv->base;
2162 uintptr_t finvivsr;
2163 uint32_t channel_bit;
2164 uint64_t timeout;
2165
2166 if (channel < __WORD_BIT) {
2167 finvivsr = rcc_base + RCC_FINDIVSR1;
2168 channel_bit = BIT(channel);
2169 } else {
2170 finvivsr = rcc_base + RCC_FINDIVSR2;
2171 channel_bit = BIT(channel - __WORD_BIT);
2172 }
2173
2174 timeout = timeout_init_us(CLKDIV_TIMEOUT);
2175 while ((mmio_read_32(finvivsr) & channel_bit) != 0U) {
2176 if (timeout_elapsed(timeout)) {
2177 EARLY_ERROR("Final divider status: %x\n",
2178 mmio_read_32(finvivsr));
2179 return -ETIMEDOUT;
2180 }
2181 }
2182
2183 return 0;
2184 }
2185
wait_xbar_sts(uint16_t channel)2186 static int wait_xbar_sts(uint16_t channel)
2187 {
2188 struct stm32_clk_priv *priv = clk_stm32_get_priv();
2189 uintptr_t rcc_base = priv->base;
2190 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4U * channel);
2191 uint64_t timeout;
2192
2193 timeout = timeout_init_us(CLKDIV_TIMEOUT);
2194 while ((mmio_read_32(xbar_cfgr) & RCC_XBAR0CFGR_XBAR0STS) != 0U) {
2195 if (timeout_elapsed(timeout)) {
2196 EARLY_ERROR("XBAR%uCFGR: %x\n", channel,
2197 mmio_read_32(xbar_cfgr));
2198 return -ETIMEDOUT;
2199 }
2200 }
2201
2202 return 0;
2203 }
2204
flexclkgen_config_channel(uint16_t channel,unsigned int clk_src,unsigned int prediv,unsigned int findiv)2205 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src,
2206 unsigned int prediv, unsigned int findiv)
2207 {
2208 struct stm32_clk_priv *priv = clk_stm32_get_priv();
2209 uintptr_t rcc_base = priv->base;
2210
2211 if (wait_predivsr(channel) != 0) {
2212 panic();
2213 }
2214
2215 mmio_clrsetbits_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel),
2216 RCC_PREDIV0CFGR_PREDIV0_MASK,
2217 prediv);
2218
2219 if (wait_predivsr(channel) != 0) {
2220 panic();
2221 }
2222
2223 if (wait_findivsr(channel) != 0) {
2224 panic();
2225 }
2226
2227 mmio_clrsetbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel),
2228 RCC_FINDIV0CFGR_FINDIV0_MASK,
2229 findiv);
2230
2231 if (wait_findivsr(channel) != 0) {
2232 panic();
2233 }
2234
2235 if (wait_xbar_sts(channel) != 0) {
2236 panic();
2237 }
2238
2239 mmio_clrsetbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel),
2240 RCC_XBARxCFGR_XBARxSEL_MASK,
2241 clk_src);
2242 mmio_setbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel),
2243 RCC_XBARxCFGR_XBARxEN);
2244
2245 if (wait_xbar_sts(channel) != 0) {
2246 panic();
2247 }
2248 }
2249
stm32mp2_clk_flexgen_configure(struct stm32_clk_priv * priv)2250 static int stm32mp2_clk_flexgen_configure(struct stm32_clk_priv *priv)
2251 {
2252 struct stm32_clk_platdata *pdata = priv->pdata;
2253 uint32_t i;
2254
2255 for (i = 0U; i < pdata->nflexgen; i++) {
2256 uint32_t val = pdata->flexgen[i];
2257 uint32_t cmd, cmd_data;
2258 unsigned int channel, clk_src, pdiv, fdiv;
2259
2260 cmd = (val & CMD_MASK) >> CMD_SHIFT;
2261 cmd_data = val & ~CMD_MASK;
2262
2263 if (cmd != CMD_FLEXGEN) {
2264 continue;
2265 }
2266
2267 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT;
2268 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT;
2269 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT;
2270 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT;
2271
2272 switch (channel) {
2273 case 33U: /* STGEN */
2274 break;
2275
2276 default:
2277 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv);
2278 break;
2279 }
2280 }
2281
2282 return 0;
2283 }
2284
stm32_enable_oscillator_hse(struct stm32_clk_priv * priv)2285 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv)
2286 {
2287 struct stm32_clk_platdata *pdata = priv->pdata;
2288 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE];
2289 bool digbyp = osci->digbyp;
2290 bool bypass = osci->bypass;
2291 bool css = osci->css;
2292
2293 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) {
2294 return;
2295 }
2296
2297 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass);
2298
2299 _clk_stm32_enable(priv, _CK_HSE);
2300
2301 clk_oscillator_set_css(priv, _CK_HSE, css);
2302 }
2303
stm32_enable_oscillator_lse(struct stm32_clk_priv * priv)2304 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv)
2305 {
2306 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE);
2307 struct stm32_clk_platdata *pdata = priv->pdata;
2308 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
2309 bool digbyp = osci->digbyp;
2310 bool bypass = osci->bypass;
2311 uint8_t drive = osci->drive;
2312
2313 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) {
2314 return;
2315 }
2316
2317 /* Do not reconfigure LSE if already enabled */
2318 if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) {
2319 return;
2320 }
2321
2322 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);
2323
2324 clk_oscillator_set_drive(priv, _CK_LSE, drive);
2325
2326 _clk_stm32_gate_enable(priv, osc_data->gate_id);
2327 }
2328
stm32mp2_clk_switch_to_hsi(struct stm32_clk_priv * priv)2329 static int stm32mp2_clk_switch_to_hsi(struct stm32_clk_priv *priv)
2330 {
2331 stm32mp2_a35_ss_on_hsi();
2332 stm32mp2_clk_muxsel_on_hsi(priv);
2333 stm32mp2_clk_xbar_on_hsi(priv);
2334
2335 return 0;
2336 }
2337
stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv * priv)2338 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv)
2339 {
2340 int ret = 0;
2341
2342 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) {
2343 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);
2344 }
2345
2346 return ret;
2347 }
2348
stm32_enable_oscillator_msi(struct stm32_clk_priv * priv)2349 static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)
2350 {
2351 #if !STM32MP21
2352 struct stm32_clk_platdata *pdata = priv->pdata;
2353 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
2354 int err;
2355
2356 err = clk_stm32_osc_msi_set_rate(priv, _CK_MSI, osci->freq, 0);
2357 if (err != 0) {
2358 EARLY_ERROR("Invalid rate %lu MHz for MSI ! (4 or 16 only)\n",
2359 osci->freq / 1000000U);
2360 panic();
2361 }
2362 #endif /* !STM32MP21 */
2363
2364 _clk_stm32_enable(priv, _CK_MSI);
2365 }
2366
stm32_clk_oscillators_enable(struct stm32_clk_priv * priv)2367 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv)
2368 {
2369 stm32_enable_oscillator_hse(priv);
2370 stm32_enable_oscillator_lse(priv);
2371 stm32_enable_oscillator_msi(priv);
2372 _clk_stm32_enable(priv, _CK_LSI);
2373 }
2374
stm32_clk_configure_div(struct stm32_clk_priv * priv,uint32_t data)2375 static int stm32_clk_configure_div(struct stm32_clk_priv *priv, uint32_t data)
2376 {
2377 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT;
2378 int div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
2379
2380 return clk_stm32_set_div(priv, div_id, div_n);
2381 }
2382
stm32_clk_configure_mux(struct stm32_clk_priv * priv,uint32_t data)2383 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data)
2384 {
2385 int mux_id = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
2386 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
2387
2388 return clk_mux_set_parent(priv, mux_id, sel);
2389 }
2390
stm32_clk_configure(struct stm32_clk_priv * priv,uint32_t val)2391 static int stm32_clk_configure(struct stm32_clk_priv *priv, uint32_t val)
2392 {
2393 uint32_t cmd = (val & CMD_MASK) >> CMD_SHIFT;
2394 uint32_t cmd_data = val & ~CMD_MASK;
2395 int ret = -1;
2396
2397 switch (cmd) {
2398 case CMD_DIV:
2399 ret = stm32_clk_configure_div(priv, cmd_data);
2400 break;
2401
2402 case CMD_MUX:
2403 ret = stm32_clk_configure_mux(priv, cmd_data);
2404 break;
2405
2406 default:
2407 EARLY_ERROR("%s: cmd unknown ! : 0x%x\n", __func__, val);
2408 break;
2409 }
2410
2411 return ret;
2412 }
2413
stm32_clk_bus_configure(struct stm32_clk_priv * priv)2414 static int stm32_clk_bus_configure(struct stm32_clk_priv *priv)
2415 {
2416 struct stm32_clk_platdata *pdata = priv->pdata;
2417 uint32_t i;
2418
2419 for (i = 0; i < pdata->nbusclk; i++) {
2420 int ret;
2421
2422 ret = stm32_clk_configure(priv, pdata->busclk[i]);
2423 if (ret != 0) {
2424 return ret;
2425 }
2426 }
2427
2428 return 0;
2429 }
2430
stm32_clk_kernel_configure(struct stm32_clk_priv * priv)2431 static int stm32_clk_kernel_configure(struct stm32_clk_priv *priv)
2432 {
2433 struct stm32_clk_platdata *pdata = priv->pdata;
2434 uint32_t i;
2435
2436 for (i = 0U; i < pdata->nkernelclk; i++) {
2437 int ret;
2438
2439 ret = stm32_clk_configure(priv, pdata->kernelclk[i]);
2440 if (ret != 0) {
2441 return ret;
2442 }
2443 }
2444
2445 return 0;
2446 }
2447
stm32mp2_init_clock_tree(void)2448 static int stm32mp2_init_clock_tree(void)
2449 {
2450 struct stm32_clk_priv *priv = clk_stm32_get_priv();
2451 int ret;
2452
2453 /* Set timer with STGEN without changing its clock source */
2454 stm32mp_stgen_restore_rate();
2455 generic_delay_timer_init();
2456
2457 stm32_clk_oscillators_enable(priv);
2458
2459 /* Come back to HSI */
2460 ret = stm32mp2_clk_switch_to_hsi(priv);
2461 if (ret != 0) {
2462 panic();
2463 }
2464
2465 ret = stm32mp2_clk_pll_configure(priv);
2466 if (ret != 0) {
2467 panic();
2468 }
2469
2470 /* Wait LSE ready before to use it */
2471 ret = stm32_clk_oscillators_wait_lse_ready(priv);
2472 if (ret != 0) {
2473 panic();
2474 }
2475
2476 ret = stm32mp2_clk_flexgen_configure(priv);
2477 if (ret != 0) {
2478 panic();
2479 }
2480
2481 ret = stm32_clk_bus_configure(priv);
2482 if (ret != 0) {
2483 panic();
2484 }
2485
2486 ret = stm32_clk_kernel_configure(priv);
2487 if (ret != 0) {
2488 panic();
2489 }
2490
2491 return 0;
2492 }
2493
clk_stm32_parse_oscillator_fdt(void * fdt,int node,const char * name,struct stm32_osci_dt_cfg * osci)2494 static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name,
2495 struct stm32_osci_dt_cfg *osci)
2496 {
2497 int subnode = 0;
2498
2499 /* Default value oscillator not found, freq=0 */
2500 osci->freq = 0;
2501
2502 fdt_for_each_subnode(subnode, fdt, node) {
2503 const char *cchar = NULL;
2504 const fdt32_t *cuint = NULL;
2505 int ret = 0;
2506
2507 cchar = fdt_get_name(fdt, subnode, &ret);
2508 if (cchar == NULL) {
2509 return ret;
2510 }
2511
2512 if (strncmp(cchar, name, (size_t)ret) ||
2513 fdt_get_status(subnode) == DT_DISABLED) {
2514 continue;
2515 }
2516
2517 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
2518 if (cuint == NULL) {
2519 return ret;
2520 }
2521
2522 osci->freq = fdt32_to_cpu(*cuint);
2523
2524 if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) {
2525 osci->bypass = true;
2526 }
2527
2528 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) {
2529 osci->digbyp = true;
2530 }
2531
2532 if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) {
2533 osci->css = true;
2534 }
2535
2536 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH);
2537
2538 return 0;
2539 }
2540
2541 return 0;
2542 }
2543
stm32_clk_parse_fdt_all_oscillator(void * fdt,struct stm32_clk_platdata * pdata)2544 static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata)
2545 {
2546 int fdt_err = 0;
2547 uint32_t i = 0;
2548 int node = 0;
2549
2550 node = fdt_path_offset(fdt, "/clocks");
2551 if (node < 0) {
2552 return -FDT_ERR_NOTFOUND;
2553 }
2554
2555 for (i = 0; i < pdata->nosci; i++) {
2556 const char *name = NULL;
2557
2558 name = clk_stm32_get_oscillator_name((enum stm32_osc)i);
2559 if (name == NULL) {
2560 continue;
2561 }
2562
2563 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]);
2564 if (fdt_err < 0) {
2565 panic();
2566 }
2567 }
2568
2569 return 0;
2570 }
2571
clk_stm32_parse_pll_fdt(void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)2572 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2573 {
2574 const fdt32_t *cuint = NULL;
2575 int subnode_pll = 0;
2576 uint32_t val = 0;
2577 int err = 0;
2578
2579 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
2580 if (!cuint) {
2581 return -FDT_ERR_NOTFOUND;
2582 }
2583
2584 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
2585 if (subnode_pll < 0) {
2586 return -FDT_ERR_NOTFOUND;
2587 }
2588
2589 err = fdt_read_uint32_array(fdt, subnode_pll, "cfg", (int)PLLCFG_NB, pll->cfg);
2590 if (err != 0) {
2591 return err;
2592 }
2593
2594 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", (int)PLLCSG_NB, pll->csg);
2595
2596 pll->csg_enabled = (err == 0);
2597
2598 if (err == -FDT_ERR_NOTFOUND) {
2599 err = 0;
2600 }
2601
2602 if (err != 0) {
2603 return err;
2604 }
2605
2606 pll->enabled = true;
2607
2608 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0);
2609
2610 pll->src = UINT32_MAX;
2611
2612 err = fdt_read_uint32(fdt, subnode_pll, "src", &val);
2613 if (err == 0) {
2614 pll->src = val;
2615 }
2616
2617 return 0;
2618 }
2619
2620 #define RCC_PLL_NAME_SIZE 12
2621
stm32_clk_parse_fdt_all_pll(void * fdt,int node,struct stm32_clk_platdata * pdata)2622 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata)
2623 {
2624 unsigned int i = 0;
2625
2626 for (i = _PLL1; i < pdata->npll; i++) {
2627 struct stm32_pll_dt_cfg *pll = pdata->pll + i;
2628 char name[RCC_PLL_NAME_SIZE];
2629 int subnode = 0;
2630 int err = 0;
2631
2632 #if STM32MP21
2633 if (i == _PLL3) {
2634 continue;
2635 }
2636 #endif
2637 snprintf(name, sizeof(name), "st,pll-%u", i + 1);
2638
2639 subnode = fdt_subnode_offset(fdt, node, name);
2640 if (!fdt_check_node(subnode)) {
2641 continue;
2642 }
2643
2644 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);
2645 if (err != 0) {
2646 panic();
2647 }
2648 }
2649
2650 return 0;
2651 }
2652
stm32_clk_parse_fdt(struct stm32_clk_platdata * pdata)2653 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata)
2654 {
2655 void *fdt = NULL;
2656 int node;
2657 int err;
2658
2659 if (fdt_get_address(&fdt) == 0) {
2660 return -ENOENT;
2661 }
2662
2663 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
2664 if (node < 0) {
2665 panic();
2666 }
2667
2668 err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata);
2669 if (err != 0) {
2670 return err;
2671 }
2672
2673 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
2674 if (err != 0) {
2675 return err;
2676 }
2677
2678 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,busclk", pdata->busclk, &pdata->nbusclk);
2679 if (err != 0) {
2680 return err;
2681 }
2682
2683 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,flexgen", pdata->flexgen,
2684 &pdata->nflexgen);
2685 if (err != 0) {
2686 return err;
2687 }
2688
2689 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,kerclk", pdata->kernelclk,
2690 &pdata->nkernelclk);
2691 if (err != 0) {
2692 return err;
2693 }
2694
2695 return 0;
2696 }
2697 #endif /* IMAGE_BL2 */
2698
2699 static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR];
2700
2701 static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB];
2702
2703 #define DT_FLEXGEN_CLK_MAX 64
2704 static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX];
2705
2706 #if STM32MP21
2707 #define DT_BUS_CLK_MAX 7
2708 #else /* STM32MP21 */
2709 #define DT_BUS_CLK_MAX 6
2710 #endif /* STM32MP21 */
2711 static uint32_t mp2_busclk[DT_BUS_CLK_MAX];
2712
2713 #define DT_KERNEL_CLK_MAX 20
2714 static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX];
2715
2716 static struct stm32_clk_platdata stm32mp2_pdata = {
2717 .osci = mp2_osci,
2718 .nosci = NB_OSCILLATOR,
2719 .pll = mp2_pll,
2720 .npll = _PLL_NB,
2721 .flexgen = mp2_flexgen,
2722 .nflexgen = DT_FLEXGEN_CLK_MAX,
2723 .busclk = mp2_busclk,
2724 .nbusclk = DT_BUS_CLK_MAX,
2725 .kernelclk = mp2_kernelclk,
2726 .nkernelclk = DT_KERNEL_CLK_MAX,
2727 };
2728
2729 static uint8_t refcounts_mp2[CK_LAST];
2730
2731 static struct stm32_clk_priv stm32mp2_clock_data = {
2732 .base = RCC_BASE,
2733 .num = ARRAY_SIZE(stm32mp2_clk),
2734 .clks = stm32mp2_clk,
2735 .parents = parent_mp2,
2736 .nb_parents = ARRAY_SIZE(parent_mp2),
2737 .gates = gates_mp2,
2738 .nb_gates = ARRAY_SIZE(gates_mp2),
2739 .div = dividers_mp2,
2740 .nb_div = ARRAY_SIZE(dividers_mp2),
2741 .osci_data = stm32mp2_osc_data,
2742 .nb_osci_data = ARRAY_SIZE(stm32mp2_osc_data),
2743 .gate_refcounts = refcounts_mp2,
2744 .pdata = &stm32mp2_pdata,
2745 .ops_array = ops_array_mp2,
2746 };
2747
stm32mp2_clk_init(void)2748 int stm32mp2_clk_init(void)
2749 {
2750 uintptr_t base = RCC_BASE;
2751 int ret;
2752
2753 #ifdef IMAGE_BL2
2754 ret = stm32_clk_parse_fdt(&stm32mp2_pdata);
2755 if (ret != 0) {
2756 return ret;
2757 }
2758 #endif
2759
2760 ret = clk_stm32_init(&stm32mp2_clock_data, base);
2761 if (ret != 0) {
2762 return ret;
2763 }
2764
2765 #ifdef IMAGE_BL2
2766 ret = stm32mp2_init_clock_tree();
2767 if (ret != 0) {
2768 return ret;
2769 }
2770
2771 clk_stm32_enable_critical_clocks();
2772 #endif
2773
2774 return 0;
2775 }
2776
stm32mp2_pll1_disable(void)2777 int stm32mp2_pll1_disable(void)
2778 {
2779 #ifdef IMAGE_BL2
2780 return -EPERM;
2781 #else
2782 uintptr_t a35_ss_address = A35SSC_BASE;
2783 uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;
2784
2785 stm32mp2_a35_ss_on_hsi();
2786
2787 mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD);
2788
2789 return 0;
2790 #endif
2791 }
2792