1 /*
2 * Copyright (C) 2018-2026, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <stdint.h>
10 #include <stdio.h>
11
12 #include <arch.h>
13 #include <arch_helpers.h>
14 #include <common/debug.h>
15 #include <common/fdt_wrappers.h>
16 #include <drivers/clk.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/st/stm32mp_clkfunc.h>
19 #include <drivers/st/stm32mp1_clk.h>
20 #include <drivers/st/stm32mp1_rcc.h>
21 #include <dt-bindings/clock/stm32mp1-clksrc.h>
22 #include <lib/mmio.h>
23 #include <lib/spinlock.h>
24 #include <lib/utils_def.h>
25 #include <libfdt.h>
26 #include <plat/common/platform.h>
27
28 #include <platform_def.h>
29
30 enum stm32mp1_pllcfg {
31 PLLCFG_M,
32 PLLCFG_N,
33 PLL_DIV_MN_NB,
34 PLLCFG_P = PLL_DIV_MN_NB,
35 PLLCFG_Q,
36 PLLCFG_R,
37 PLLCFG_O,
38 PLLCFG_NB
39 };
40
41 #define PLL_DIV_MN_NB 2
42 #define PLL_DIV_PQR_NB 3
43
44 enum stm32mp1_pllcsg {
45 PLLCSG_MOD_PER,
46 PLLCSG_INC_STEP,
47 PLLCSG_SSCG_MODE,
48 PLLCSG_NB
49 };
50
51 struct stm32_pll_dt_cfg {
52 bool status;
53 uint32_t src;
54 uint32_t cfg[PLLCFG_NB];
55 uint32_t frac;
56 bool csg_enabled;
57 uint32_t csg[PLLCSG_NB];
58 };
59
60 struct stm32_clk_platdata {
61 uint32_t npll;
62 struct stm32_pll_dt_cfg *pll;
63 uint32_t nclksrc;
64 uint32_t *clksrc;
65 uint32_t nclkdiv;
66 uint32_t *clkdiv;
67 bool lse_css;
68 };
69
70 struct stm32_clk_priv {
71 uintptr_t base;
72 const struct mux_cfg *parents;
73 const uint32_t nb_parents;
74 const struct div_cfg *div;
75 const uint32_t nb_div;
76 void *pdata;
77 };
78
79 static struct stm32_clk_priv *stm32_clock_data;
80
clk_stm32_get_priv(void)81 static struct stm32_clk_priv *clk_stm32_get_priv(void)
82 {
83 return stm32_clock_data;
84 }
85
clk_stm32_init(struct stm32_clk_priv * priv,uintptr_t base)86 static int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base)
87 {
88 stm32_clock_data = priv;
89
90 priv->base = base;
91
92 return 0;
93 }
94
95 #define MAX_HSI_HZ 64000000
96 #define USB_PHY_48_MHZ 48000000
97
98 #define TIMEOUT_US_200MS U(200000)
99 #define TIMEOUT_US_2S U(2000000)
100
101 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
102 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
103 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
104 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS
105 #define OSCRDY_TIMEOUT TIMEOUT_US_2S
106
107 struct mux_cfg {
108 uint16_t offset;
109 uint8_t shift;
110 uint8_t width;
111 uint8_t bitrdy;
112 };
113
114 struct div_cfg {
115 uint16_t offset;
116 uint8_t shift;
117 uint8_t width;
118 uint8_t bitrdy;
119 };
120
121 #define DIV_NO_BIT_RDY UINT8_MAX
122
123 #define DIV_CFG(_id, _offset, _shift, _width, _bitrdy)\
124 [(_id)] = {\
125 .offset = (_offset),\
126 .shift = (_shift),\
127 .width = (_width),\
128 .bitrdy = (_bitrdy),\
129 }
130
131 static const struct div_cfg dividers_mp15[] = {
132 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 31),
133 DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 31),
134 DIV_CFG(DIV_MCU, RCC_MCUDIVR, 0, 4, 31),
135 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 31),
136 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 31),
137 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 31),
138 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 31),
139 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 31),
140 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, DIV_NO_BIT_RDY),
141 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, DIV_NO_BIT_RDY),
142 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, DIV_NO_BIT_RDY),
143 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, DIV_NO_BIT_RDY),
144 DIV_CFG(DIV_ETHPTP, RCC_ETHCKSELR, 4, 4, DIV_NO_BIT_RDY),
145 };
146
147 /*
148 * MUX CONFIG
149 */
150
151 #define MUX_NO_BIT_RDY UINT8_MAX
152
153 #define MUXRDY_CFG(_id, _offset, _shift, _width, _bitrdy)\
154 [(_id)] = {\
155 .offset = (_offset),\
156 .shift = (_shift),\
157 .width = (_width),\
158 .bitrdy = (_bitrdy),\
159 }
160
161 #define MUX_CFG(_id, _offset, _shift, _width)\
162 MUXRDY_CFG(_id, _offset, _shift, _width, MUX_NO_BIT_RDY)
163
164 static const struct mux_cfg parent_mp15[MUX_NB] = {
165 MUX_CFG(MUX_PLL12, RCC_RCK12SELR, 0, 2),
166 MUX_CFG(MUX_PLL3, RCC_RCK3SELR, 0, 2),
167 MUX_CFG(MUX_PLL4, RCC_RCK4SELR, 0, 2),
168 MUX_CFG(MUX_CKPER, RCC_CPERCKSELR, 0, 2),
169 MUXRDY_CFG(MUX_MPU, RCC_MPCKSELR, 0, 2, 31),
170 MUXRDY_CFG(MUX_AXI, RCC_ASSCKSELR, 0, 3, 31),
171 MUXRDY_CFG(MUX_MCU, RCC_MSSCKSELR, 0, 2, 31),
172 MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2),
173 MUX_CFG(MUX_SDMMC12, RCC_SDMMC12CKSELR, 0, 3),
174 MUX_CFG(MUX_SPI2S23, RCC_SPI2S23CKSELR, 0, 3),
175 MUX_CFG(MUX_SPI45, RCC_SPI45CKSELR, 0, 3),
176 MUX_CFG(MUX_I2C12, RCC_I2C12CKSELR, 0, 3),
177 MUX_CFG(MUX_I2C35, RCC_I2C35CKSELR, 0, 3),
178 MUX_CFG(MUX_LPTIM23, RCC_LPTIM23CKSELR, 0, 3),
179 MUX_CFG(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3),
180 MUX_CFG(MUX_UART24, RCC_UART24CKSELR, 0, 3),
181 MUX_CFG(MUX_UART35, RCC_UART35CKSELR, 0, 3),
182 MUX_CFG(MUX_UART78, RCC_UART78CKSELR, 0, 3),
183 MUX_CFG(MUX_SAI1, RCC_SAI1CKSELR, 0, 3),
184 MUX_CFG(MUX_ETH, RCC_ETHCKSELR, 0, 2),
185 MUX_CFG(MUX_I2C46, RCC_I2C46CKSELR, 0, 3),
186 MUX_CFG(MUX_RNG2, RCC_RNG2CKSELR, 0, 2),
187 MUX_CFG(MUX_SDMMC3, RCC_SDMMC3CKSELR, 0, 3),
188 MUX_CFG(MUX_FMC, RCC_FMCCKSELR, 0, 2),
189 MUX_CFG(MUX_QSPI, RCC_QSPICKSELR, 0, 2),
190 MUX_CFG(MUX_USBPHY, RCC_USBCKSELR, 0, 2),
191 MUX_CFG(MUX_USBO, RCC_USBCKSELR, 4, 1),
192 MUX_CFG(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2),
193 MUX_CFG(MUX_SPI2S1, RCC_SPI2S1CKSELR, 0, 3),
194 MUX_CFG(MUX_CEC, RCC_CECCKSELR, 0, 2),
195 MUX_CFG(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3),
196 MUX_CFG(MUX_UART6, RCC_UART6CKSELR, 0, 3),
197 MUX_CFG(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2),
198 MUX_CFG(MUX_SAI2, RCC_SAI2CKSELR, 0, 3),
199 MUX_CFG(MUX_SAI3, RCC_SAI3CKSELR, 0, 3),
200 MUX_CFG(MUX_SAI4, RCC_SAI4CKSELR, 0, 3),
201 MUX_CFG(MUX_ADC, RCC_ADCCKSELR, 0, 2),
202 MUX_CFG(MUX_DSI, RCC_DSICKSELR, 0, 1),
203 MUX_CFG(MUX_RNG1, RCC_RNG1CKSELR, 0, 2),
204 MUX_CFG(MUX_STGEN, RCC_STGENCKSELR, 0, 2),
205 MUX_CFG(MUX_UART1, RCC_UART1CKSELR, 0, 3),
206 MUX_CFG(MUX_SPI6, RCC_SPI6CKSELR, 0, 3),
207 MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 3),
208 MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 3),
209 };
210
211 #define MASK_WIDTH_SHIFT(_width, _shift) \
212 GENMASK(((_width) + (_shift) - 1U), (_shift))
213
clk_mux_get_parent(struct stm32_clk_priv * priv,uint32_t mux_id)214 int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id)
215 {
216 const struct mux_cfg *mux;
217 uint32_t mask;
218
219 if (mux_id >= priv->nb_parents) {
220 panic();
221 }
222
223 mux = &priv->parents[mux_id];
224
225 mask = MASK_WIDTH_SHIFT(mux->width, mux->shift);
226
227 return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift;
228 }
229
clk_mux_set_parent(struct stm32_clk_priv * priv,uint16_t pid,uint8_t sel)230 static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel)
231 {
232 const struct mux_cfg *mux = &priv->parents[pid];
233 uintptr_t address = priv->base + mux->offset;
234 uint32_t mask;
235 uint64_t timeout;
236
237 mask = MASK_WIDTH_SHIFT(mux->width, mux->shift);
238
239 mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask);
240
241 if (mux->bitrdy == MUX_NO_BIT_RDY) {
242 return 0;
243 }
244
245 timeout = timeout_init_us(CLKSRC_TIMEOUT);
246
247 mask = BIT(mux->bitrdy);
248
249 while ((mmio_read_32(address) & mask) == 0U) {
250 if (timeout_elapsed(timeout)) {
251 return -ETIMEDOUT;
252 }
253 }
254
255 return 0;
256 }
257
stm32_clk_configure_mux(struct stm32_clk_priv * priv,uint32_t val)258 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t val)
259 {
260 uint32_t data = val & CMD_DATA_MASK;
261 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
262 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
263
264 return clk_mux_set_parent(priv, mux, sel);
265 }
266
clk_stm32_set_div(struct stm32_clk_priv * priv,uint32_t div_id,uint32_t value)267 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value)
268 {
269 const struct div_cfg *divider;
270 uintptr_t address;
271 uint64_t timeout;
272 uint32_t mask;
273
274 if (div_id >= priv->nb_div) {
275 panic();
276 }
277
278 divider = &priv->div[div_id];
279 address = priv->base + divider->offset;
280
281 mask = MASK_WIDTH_SHIFT(divider->width, divider->shift);
282 mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask);
283
284 if (divider->bitrdy == DIV_NO_BIT_RDY) {
285 return 0;
286 }
287
288 timeout = timeout_init_us(CLKSRC_TIMEOUT);
289 mask = BIT(divider->bitrdy);
290
291 while ((mmio_read_32(address) & mask) == 0U) {
292 if (timeout_elapsed(timeout)) {
293 return -ETIMEDOUT;
294 }
295 }
296
297 return 0;
298 }
299
300 const char *stm32mp_osc_node_label[NB_OSC] = {
301 [_LSI] = "clk-lsi",
302 [_LSE] = "clk-lse",
303 [_HSI] = "clk-hsi",
304 [_HSE] = "clk-hse",
305 [_CSI] = "clk-csi",
306 [_I2S_CKIN] = "i2s_ckin",
307 };
308
309 enum stm32mp1_parent_id {
310 /* Oscillators are defined in enum stm32mp_osc_id */
311
312 /* Other parent source */
313 _HSI_KER = NB_OSC,
314 _HSE_KER,
315 _HSE_KER_DIV2,
316 _HSE_RTC,
317 _CSI_KER,
318 _PLL1_P,
319 _PLL1_Q,
320 _PLL1_R,
321 _PLL2_P,
322 _PLL2_Q,
323 _PLL2_R,
324 _PLL3_P,
325 _PLL3_Q,
326 _PLL3_R,
327 _PLL4_P,
328 _PLL4_Q,
329 _PLL4_R,
330 _ACLK,
331 _PCLK1,
332 _PCLK2,
333 _PCLK3,
334 _PCLK4,
335 _PCLK5,
336 _HCLK6,
337 _HCLK2,
338 _CK_PER,
339 _CK_MPU,
340 _CK_MCU,
341 _USB_PHY_48,
342 _PARENT_NB,
343 _UNKNOWN_ID = 0xff,
344 };
345
346 /* Lists only the parent clock we are interested in */
347 enum stm32mp1_parent_sel {
348 _I2C12_SEL,
349 _I2C35_SEL,
350 _STGEN_SEL,
351 _I2C46_SEL,
352 _SPI6_SEL,
353 _UART1_SEL,
354 _RNG1_SEL,
355 _UART6_SEL,
356 _UART24_SEL,
357 _UART35_SEL,
358 _UART78_SEL,
359 _SDMMC12_SEL,
360 _SDMMC3_SEL,
361 _QSPI_SEL,
362 _FMC_SEL,
363 _AXIS_SEL,
364 _MCUS_SEL,
365 _USBPHY_SEL,
366 _USBO_SEL,
367 _MPU_SEL,
368 _CKPER_SEL,
369 _RTC_SEL,
370 _PARENT_SEL_NB,
371 _UNKNOWN_SEL = 0xff,
372 };
373
374 /* State the parent clock ID straight related to a clock */
375 static const uint8_t parent_id_clock_id[_PARENT_NB] = {
376 [_HSE] = CK_HSE,
377 [_HSI] = CK_HSI,
378 [_CSI] = CK_CSI,
379 [_LSE] = CK_LSE,
380 [_LSI] = CK_LSI,
381 [_I2S_CKIN] = _UNKNOWN_ID,
382 [_USB_PHY_48] = _UNKNOWN_ID,
383 [_HSI_KER] = CK_HSI,
384 [_HSE_KER] = CK_HSE,
385 [_HSE_KER_DIV2] = CK_HSE_DIV2,
386 [_HSE_RTC] = _UNKNOWN_ID,
387 [_CSI_KER] = CK_CSI,
388 [_PLL1_P] = PLL1_P,
389 [_PLL1_Q] = PLL1_Q,
390 [_PLL1_R] = PLL1_R,
391 [_PLL2_P] = PLL2_P,
392 [_PLL2_Q] = PLL2_Q,
393 [_PLL2_R] = PLL2_R,
394 [_PLL3_P] = PLL3_P,
395 [_PLL3_Q] = PLL3_Q,
396 [_PLL3_R] = PLL3_R,
397 [_PLL4_P] = PLL4_P,
398 [_PLL4_Q] = PLL4_Q,
399 [_PLL4_R] = PLL4_R,
400 [_ACLK] = CK_AXI,
401 [_PCLK1] = CK_AXI,
402 [_PCLK2] = CK_AXI,
403 [_PCLK3] = CK_AXI,
404 [_PCLK4] = CK_AXI,
405 [_PCLK5] = CK_AXI,
406 [_CK_PER] = CK_PER,
407 [_CK_MPU] = CK_MPU,
408 [_CK_MCU] = CK_MCU,
409 };
410
clock_id2parent_id(unsigned long id)411 static unsigned int clock_id2parent_id(unsigned long id)
412 {
413 unsigned int n;
414
415 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) {
416 if (parent_id_clock_id[n] == id) {
417 return n;
418 }
419 }
420
421 return _UNKNOWN_ID;
422 }
423
424 enum stm32mp1_pll_id {
425 _PLL1,
426 _PLL2,
427 _PLL3,
428 _PLL4,
429 _PLL_NB
430 };
431
432 enum stm32mp1_div_id {
433 _DIV_P,
434 _DIV_Q,
435 _DIV_R,
436 _DIV_NB,
437 };
438
439 enum stm32mp1_clksrc_id {
440 CLKSRC_MPU,
441 CLKSRC_AXI,
442 CLKSRC_MCU,
443 CLKSRC_PLL12,
444 CLKSRC_PLL3,
445 CLKSRC_PLL4,
446 CLKSRC_RTC,
447 CLKSRC_MCO1,
448 CLKSRC_MCO2,
449 CLKSRC_NB
450 };
451
452 enum stm32mp1_clkdiv_id {
453 CLKDIV_MPU,
454 CLKDIV_AXI,
455 CLKDIV_MCU,
456 CLKDIV_APB1,
457 CLKDIV_APB2,
458 CLKDIV_APB3,
459 CLKDIV_APB4,
460 CLKDIV_APB5,
461 CLKDIV_RTC,
462 CLKDIV_MCO1,
463 CLKDIV_MCO2,
464 CLKDIV_NB
465 };
466
467 enum stm32mp1_plltype {
468 PLL_800,
469 PLL_1600,
470 PLL_TYPE_NB
471 };
472
473 struct stm32mp1_pll {
474 uint8_t refclk_min;
475 uint8_t refclk_max;
476 };
477
478 struct stm32mp1_clk_gate {
479 uint16_t offset;
480 uint8_t bit;
481 uint8_t index;
482 uint8_t set_clr;
483 uint8_t secure;
484 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
485 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
486 };
487
488 struct stm32mp1_clk_sel {
489 uint16_t offset;
490 uint8_t src;
491 uint8_t msk;
492 uint8_t nb_parent;
493 const uint8_t *parent;
494 };
495
496 #define REFCLK_SIZE 4
497 struct stm32mp1_clk_pll {
498 enum stm32mp1_plltype plltype;
499 uint16_t rckxselr;
500 uint16_t pllxcfgr1;
501 uint16_t pllxcfgr2;
502 uint16_t pllxfracr;
503 uint16_t pllxcr;
504 uint16_t pllxcsgr;
505 enum stm32mp_osc_id refclk[REFCLK_SIZE];
506 };
507
508 /* Clocks with selectable source and non set/clr register access */
509 #define _CLK_SELEC(sec, off, b, idx, s) \
510 { \
511 .offset = (off), \
512 .bit = (b), \
513 .index = (idx), \
514 .set_clr = 0, \
515 .secure = (sec), \
516 .sel = (s), \
517 .fixed = _UNKNOWN_ID, \
518 }
519
520 /* Clocks with fixed source and non set/clr register access */
521 #define _CLK_FIXED(sec, off, b, idx, f) \
522 { \
523 .offset = (off), \
524 .bit = (b), \
525 .index = (idx), \
526 .set_clr = 0, \
527 .secure = (sec), \
528 .sel = _UNKNOWN_SEL, \
529 .fixed = (f), \
530 }
531
532 /* Clocks with selectable source and set/clr register access */
533 #define _CLK_SC_SELEC(sec, off, b, idx, s) \
534 { \
535 .offset = (off), \
536 .bit = (b), \
537 .index = (idx), \
538 .set_clr = 1, \
539 .secure = (sec), \
540 .sel = (s), \
541 .fixed = _UNKNOWN_ID, \
542 }
543
544 /* Clocks with fixed source and set/clr register access */
545 #define _CLK_SC_FIXED(sec, off, b, idx, f) \
546 { \
547 .offset = (off), \
548 .bit = (b), \
549 .index = (idx), \
550 .set_clr = 1, \
551 .secure = (sec), \
552 .sel = _UNKNOWN_SEL, \
553 .fixed = (f), \
554 }
555
556 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \
557 [_ ## _label ## _SEL] = { \
558 .offset = _rcc_selr, \
559 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \
560 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \
561 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \
562 .parent = (_parents), \
563 .nb_parent = ARRAY_SIZE(_parents) \
564 }
565
566 #define _CLK_PLL(idx, type, off1, off2, off3, \
567 off4, off5, off6, \
568 p1, p2, p3, p4) \
569 [(idx)] = { \
570 .plltype = (type), \
571 .rckxselr = (off1), \
572 .pllxcfgr1 = (off2), \
573 .pllxcfgr2 = (off3), \
574 .pllxfracr = (off4), \
575 .pllxcr = (off5), \
576 .pllxcsgr = (off6), \
577 .refclk[0] = (p1), \
578 .refclk[1] = (p2), \
579 .refclk[2] = (p3), \
580 .refclk[3] = (p4), \
581 }
582
583 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
584
585 #define SEC 1
586 #define N_S 0
587
588 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
589 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK),
590 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
591 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK),
592 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
593 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
594 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
595 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
596 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
597 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK),
598 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
599 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
600
601 #if defined(IMAGE_BL32)
602 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
603 #endif
604 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
605 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
606 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
607 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
608 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
609 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
610 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
611 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
612 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
613 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
614
615 #if defined(IMAGE_BL32)
616 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
617 #endif
618 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
619
620 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
621
622 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
623 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
624 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
625
626 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
627 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
628 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
629 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
630 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
631 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
632 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
633 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5),
634 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5),
635 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5),
636 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
637
638 #if defined(IMAGE_BL32)
639 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
640 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
641 #endif
642
643 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
644 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
645 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
646 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
647 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
648 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
649 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
650 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
651 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
652 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
653 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
654
655 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5),
656 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5),
657 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5),
658 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL),
659 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5),
660
661 #if defined(IMAGE_BL2)
662 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
663 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
664 #endif
665 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
666 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
667 #if defined(IMAGE_BL32)
668 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
669 #endif
670
671 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL),
672 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
673 };
674
675 static const uint8_t i2c12_parents[] = {
676 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
677 };
678
679 static const uint8_t i2c35_parents[] = {
680 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
681 };
682
683 static const uint8_t stgen_parents[] = {
684 _HSI_KER, _HSE_KER
685 };
686
687 static const uint8_t i2c46_parents[] = {
688 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
689 };
690
691 static const uint8_t spi6_parents[] = {
692 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
693 };
694
695 static const uint8_t usart1_parents[] = {
696 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
697 };
698
699 static const uint8_t rng1_parents[] = {
700 _CSI, _PLL4_R, _LSE, _LSI
701 };
702
703 static const uint8_t uart6_parents[] = {
704 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
705 };
706
707 static const uint8_t uart234578_parents[] = {
708 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
709 };
710
711 static const uint8_t sdmmc12_parents[] = {
712 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER
713 };
714
715 static const uint8_t sdmmc3_parents[] = {
716 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER
717 };
718
719 static const uint8_t qspi_parents[] = {
720 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
721 };
722
723 static const uint8_t fmc_parents[] = {
724 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
725 };
726
727 static const uint8_t axiss_parents[] = {
728 _HSI, _HSE, _PLL2_P
729 };
730
731 static const uint8_t mcuss_parents[] = {
732 _HSI, _HSE, _CSI, _PLL3_P
733 };
734
735 static const uint8_t usbphy_parents[] = {
736 _HSE_KER, _PLL4_R, _HSE_KER_DIV2
737 };
738
739 static const uint8_t usbo_parents[] = {
740 _PLL4_R, _USB_PHY_48
741 };
742
743 static const uint8_t mpu_parents[] = {
744 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */
745 };
746
747 static const uint8_t per_parents[] = {
748 _HSI, _HSE, _CSI,
749 };
750
751 static const uint8_t rtc_parents[] = {
752 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC
753 };
754
755 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
756 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
757 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
758 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents),
759 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents),
760 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
761 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
762 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
763 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents),
764 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents),
765 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
766 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
767 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
768 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
769 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents),
770 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents),
771 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
772 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
773 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
774 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents),
775 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents),
776 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
777 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
778 };
779
780 /* Define characteristic of PLL according type */
781 #define POST_DIVM_MIN 8000000U
782 #define POST_DIVM_MAX 16000000U
783 #define DIVM_MIN 0U
784 #define DIVM_MAX 63U
785 #define DIVN_MIN 24U
786 #define DIVN_MAX 99U
787 #define DIVP_MIN 0U
788 #define DIVP_MAX 127U
789 #define FRAC_MAX 8192U
790 #define VCO_MIN 800000000U
791 #define VCO_MAX 1600000000U
792
793 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
794 [PLL_800] = {
795 .refclk_min = 4,
796 .refclk_max = 16,
797 },
798 [PLL_1600] = {
799 .refclk_min = 8,
800 .refclk_max = 16,
801 },
802 };
803
804 /* PLLNCFGR2 register divider by output */
805 static const uint8_t pllncfgr2[_DIV_NB] = {
806 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
807 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
808 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
809 };
810
811 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
812 _CLK_PLL(_PLL1, PLL_1600,
813 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
814 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
815 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
816 _CLK_PLL(_PLL2, PLL_1600,
817 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
818 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
819 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
820 _CLK_PLL(_PLL3, PLL_800,
821 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
822 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
823 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
824 _CLK_PLL(_PLL4, PLL_800,
825 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
826 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
827 _HSI, _HSE, _CSI, _I2S_CKIN),
828 };
829
830 /* Prescaler table lookups for clock computation */
831 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
832 static const uint8_t stm32mp1_mcu_div[16] = {
833 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
834 };
835
836 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
837 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
838 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
839 static const uint8_t stm32mp1_mpu_apbx_div[8] = {
840 0, 1, 2, 3, 4, 4, 4, 4
841 };
842
843 /* div = /1 /2 /3 /4 */
844 static const uint8_t stm32mp1_axi_div[8] = {
845 1, 2, 3, 4, 4, 4, 4, 4
846 };
847
848 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = {
849 [_HSI] = "HSI",
850 [_HSE] = "HSE",
851 [_CSI] = "CSI",
852 [_LSI] = "LSI",
853 [_LSE] = "LSE",
854 [_I2S_CKIN] = "I2S_CKIN",
855 [_HSI_KER] = "HSI_KER",
856 [_HSE_KER] = "HSE_KER",
857 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
858 [_HSE_RTC] = "HSE_RTC",
859 [_CSI_KER] = "CSI_KER",
860 [_PLL1_P] = "PLL1_P",
861 [_PLL1_Q] = "PLL1_Q",
862 [_PLL1_R] = "PLL1_R",
863 [_PLL2_P] = "PLL2_P",
864 [_PLL2_Q] = "PLL2_Q",
865 [_PLL2_R] = "PLL2_R",
866 [_PLL3_P] = "PLL3_P",
867 [_PLL3_Q] = "PLL3_Q",
868 [_PLL3_R] = "PLL3_R",
869 [_PLL4_P] = "PLL4_P",
870 [_PLL4_Q] = "PLL4_Q",
871 [_PLL4_R] = "PLL4_R",
872 [_ACLK] = "ACLK",
873 [_PCLK1] = "PCLK1",
874 [_PCLK2] = "PCLK2",
875 [_PCLK3] = "PCLK3",
876 [_PCLK4] = "PCLK4",
877 [_PCLK5] = "PCLK5",
878 [_HCLK6] = "KCLK6",
879 [_HCLK2] = "HCLK2",
880 [_CK_PER] = "CK_PER",
881 [_CK_MPU] = "CK_MPU",
882 [_CK_MCU] = "CK_MCU",
883 [_USB_PHY_48] = "USB_PHY_48",
884 };
885
886 /* RCC clock device driver private */
887 static unsigned long stm32mp1_osc[NB_OSC];
888 static struct spinlock reg_lock;
889 static unsigned int gate_refcounts[NB_GATES];
890 static struct spinlock refcount_lock;
891
gate_ref(unsigned int idx)892 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
893 {
894 return &stm32mp1_clk_gate[idx];
895 }
896
897 #if defined(IMAGE_BL32)
gate_is_non_secure(const struct stm32mp1_clk_gate * gate)898 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate)
899 {
900 return gate->secure == N_S;
901 }
902 #endif
903
clk_sel_ref(unsigned int idx)904 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
905 {
906 return &stm32mp1_clk_sel[idx];
907 }
908
pll_ref(unsigned int idx)909 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
910 {
911 return &stm32mp1_clk_pll[idx];
912 }
913
stm32mp1_clk_lock(struct spinlock * lock)914 static void stm32mp1_clk_lock(struct spinlock *lock)
915 {
916 if (stm32mp_lock_available()) {
917 /* Assume interrupts are masked */
918 spin_lock(lock);
919 }
920 }
921
stm32mp1_clk_unlock(struct spinlock * lock)922 static void stm32mp1_clk_unlock(struct spinlock *lock)
923 {
924 if (stm32mp_lock_available()) {
925 spin_unlock(lock);
926 }
927 }
928
stm32mp1_rcc_is_secure(void)929 bool stm32mp1_rcc_is_secure(void)
930 {
931 uintptr_t rcc_base = stm32mp_rcc_base();
932 uint32_t mask = RCC_TZCR_TZEN;
933
934 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
935 }
936
stm32mp1_rcc_is_mckprot(void)937 bool stm32mp1_rcc_is_mckprot(void)
938 {
939 uintptr_t rcc_base = stm32mp_rcc_base();
940 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT;
941
942 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
943 }
944
stm32mp1_clk_rcc_regs_lock(void)945 void stm32mp1_clk_rcc_regs_lock(void)
946 {
947 stm32mp1_clk_lock(®_lock);
948 }
949
stm32mp1_clk_rcc_regs_unlock(void)950 void stm32mp1_clk_rcc_regs_unlock(void)
951 {
952 stm32mp1_clk_unlock(®_lock);
953 }
954
stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)955 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)
956 {
957 if (idx >= NB_OSC) {
958 return 0;
959 }
960
961 return stm32mp1_osc[idx];
962 }
963
stm32mp1_clk_get_gated_id(unsigned long id)964 static int stm32mp1_clk_get_gated_id(unsigned long id)
965 {
966 unsigned int i;
967
968 for (i = 0U; i < NB_GATES; i++) {
969 if (gate_ref(i)->index == id) {
970 return i;
971 }
972 }
973
974 ERROR("%s: clk id %lu not found\n", __func__, id);
975
976 return -EINVAL;
977 }
978
stm32mp1_clk_get_sel(int i)979 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
980 {
981 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);
982 }
983
stm32mp1_clk_get_fixed_parent(int i)984 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
985 {
986 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed);
987 }
988
stm32mp1_clk_get_parent(unsigned long id)989 static int stm32mp1_clk_get_parent(unsigned long id)
990 {
991 const struct stm32mp1_clk_sel *sel;
992 uint32_t p_sel;
993 int i;
994 enum stm32mp1_parent_id p;
995 enum stm32mp1_parent_sel s;
996 uintptr_t rcc_base = stm32mp_rcc_base();
997
998 /* Few non gateable clock have a static parent ID, find them */
999 i = (int)clock_id2parent_id(id);
1000 if (i != _UNKNOWN_ID) {
1001 return i;
1002 }
1003
1004 i = stm32mp1_clk_get_gated_id(id);
1005 if (i < 0) {
1006 panic();
1007 }
1008
1009 p = stm32mp1_clk_get_fixed_parent(i);
1010 if (p < _PARENT_NB) {
1011 return (int)p;
1012 }
1013
1014 s = stm32mp1_clk_get_sel(i);
1015 if (s == _UNKNOWN_SEL) {
1016 return -EINVAL;
1017 }
1018 if (s >= _PARENT_SEL_NB) {
1019 panic();
1020 }
1021
1022 sel = clk_sel_ref(s);
1023 p_sel = (mmio_read_32(rcc_base + sel->offset) &
1024 (sel->msk << sel->src)) >> sel->src;
1025 if (p_sel < sel->nb_parent) {
1026 return (int)sel->parent[p_sel];
1027 }
1028
1029 return -EINVAL;
1030 }
1031
stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll * pll)1032 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
1033 {
1034 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr);
1035 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
1036
1037 return stm32mp1_clk_get_fixed(pll->refclk[src]);
1038 }
1039
1040 /*
1041 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
1042 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
1043 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
1044 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
1045 */
stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll * pll)1046 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
1047 {
1048 unsigned long refclk, fvco;
1049 uint32_t cfgr1, fracr, divm, divn;
1050 uintptr_t rcc_base = stm32mp_rcc_base();
1051
1052 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
1053 fracr = mmio_read_32(rcc_base + pll->pllxfracr);
1054
1055 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
1056 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
1057
1058 refclk = stm32mp1_pll_get_fref(pll);
1059
1060 /*
1061 * With FRACV :
1062 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
1063 * Without FRACV
1064 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
1065 */
1066 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
1067 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
1068 RCC_PLLNFRACR_FRACV_SHIFT;
1069 unsigned long long numerator, denominator;
1070
1071 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
1072 numerator = refclk * numerator;
1073 denominator = ((unsigned long long)divm + 1U) << 13;
1074 fvco = (unsigned long)(numerator / denominator);
1075 } else {
1076 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
1077 }
1078
1079 return fvco;
1080 }
1081
stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,enum stm32mp1_div_id div_id)1082 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
1083 enum stm32mp1_div_id div_id)
1084 {
1085 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1086 unsigned long dfout;
1087 uint32_t cfgr2, divy;
1088
1089 if (div_id >= _DIV_NB) {
1090 return 0;
1091 }
1092
1093 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2);
1094 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
1095
1096 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
1097
1098 return dfout;
1099 }
1100
get_clock_rate(int p)1101 static unsigned long get_clock_rate(int p)
1102 {
1103 uint32_t reg, clkdiv;
1104 unsigned long clock = 0;
1105 uintptr_t rcc_base = stm32mp_rcc_base();
1106
1107 switch (p) {
1108 case _CK_MPU:
1109 /* MPU sub system */
1110 reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
1111 switch (reg & RCC_SELR_SRC_MASK) {
1112 case RCC_MPCKSELR_HSI:
1113 clock = stm32mp1_clk_get_fixed(_HSI);
1114 break;
1115 case RCC_MPCKSELR_HSE:
1116 clock = stm32mp1_clk_get_fixed(_HSE);
1117 break;
1118 case RCC_MPCKSELR_PLL:
1119 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
1120 break;
1121 case RCC_MPCKSELR_PLL_MPUDIV:
1122 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
1123
1124 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
1125 clkdiv = reg & RCC_MPUDIV_MASK;
1126 clock >>= stm32mp1_mpu_div[clkdiv];
1127 break;
1128 default:
1129 break;
1130 }
1131 break;
1132 /* AXI sub system */
1133 case _ACLK:
1134 case _HCLK2:
1135 case _HCLK6:
1136 case _PCLK4:
1137 case _PCLK5:
1138 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
1139 switch (reg & RCC_SELR_SRC_MASK) {
1140 case RCC_ASSCKSELR_HSI:
1141 clock = stm32mp1_clk_get_fixed(_HSI);
1142 break;
1143 case RCC_ASSCKSELR_HSE:
1144 clock = stm32mp1_clk_get_fixed(_HSE);
1145 break;
1146 case RCC_ASSCKSELR_PLL:
1147 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
1148 break;
1149 default:
1150 break;
1151 }
1152
1153 /* System clock divider */
1154 reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
1155 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
1156
1157 switch (p) {
1158 case _PCLK4:
1159 reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
1160 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1161 break;
1162 case _PCLK5:
1163 reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
1164 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1165 break;
1166 default:
1167 break;
1168 }
1169 break;
1170 /* MCU sub system */
1171 case _CK_MCU:
1172 case _PCLK1:
1173 case _PCLK2:
1174 case _PCLK3:
1175 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);
1176 switch (reg & RCC_SELR_SRC_MASK) {
1177 case RCC_MSSCKSELR_HSI:
1178 clock = stm32mp1_clk_get_fixed(_HSI);
1179 break;
1180 case RCC_MSSCKSELR_HSE:
1181 clock = stm32mp1_clk_get_fixed(_HSE);
1182 break;
1183 case RCC_MSSCKSELR_CSI:
1184 clock = stm32mp1_clk_get_fixed(_CSI);
1185 break;
1186 case RCC_MSSCKSELR_PLL:
1187 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
1188 break;
1189 default:
1190 break;
1191 }
1192
1193 /* MCU clock divider */
1194 reg = mmio_read_32(rcc_base + RCC_MCUDIVR);
1195 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1196
1197 switch (p) {
1198 case _PCLK1:
1199 reg = mmio_read_32(rcc_base + RCC_APB1DIVR);
1200 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1201 break;
1202 case _PCLK2:
1203 reg = mmio_read_32(rcc_base + RCC_APB2DIVR);
1204 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1205 break;
1206 case _PCLK3:
1207 reg = mmio_read_32(rcc_base + RCC_APB3DIVR);
1208 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1209 break;
1210 case _CK_MCU:
1211 default:
1212 break;
1213 }
1214 break;
1215 case _CK_PER:
1216 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
1217 switch (reg & RCC_SELR_SRC_MASK) {
1218 case RCC_CPERCKSELR_HSI:
1219 clock = stm32mp1_clk_get_fixed(_HSI);
1220 break;
1221 case RCC_CPERCKSELR_HSE:
1222 clock = stm32mp1_clk_get_fixed(_HSE);
1223 break;
1224 case RCC_CPERCKSELR_CSI:
1225 clock = stm32mp1_clk_get_fixed(_CSI);
1226 break;
1227 default:
1228 break;
1229 }
1230 break;
1231 case _HSI:
1232 case _HSI_KER:
1233 clock = stm32mp1_clk_get_fixed(_HSI);
1234 break;
1235 case _CSI:
1236 case _CSI_KER:
1237 clock = stm32mp1_clk_get_fixed(_CSI);
1238 break;
1239 case _HSE:
1240 case _HSE_KER:
1241 clock = stm32mp1_clk_get_fixed(_HSE);
1242 break;
1243 case _HSE_KER_DIV2:
1244 clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
1245 break;
1246 case _HSE_RTC:
1247 clock = stm32mp1_clk_get_fixed(_HSE);
1248 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;
1249 break;
1250 case _LSI:
1251 clock = stm32mp1_clk_get_fixed(_LSI);
1252 break;
1253 case _LSE:
1254 clock = stm32mp1_clk_get_fixed(_LSE);
1255 break;
1256 /* PLL */
1257 case _PLL1_P:
1258 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
1259 break;
1260 case _PLL1_Q:
1261 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
1262 break;
1263 case _PLL1_R:
1264 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
1265 break;
1266 case _PLL2_P:
1267 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
1268 break;
1269 case _PLL2_Q:
1270 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
1271 break;
1272 case _PLL2_R:
1273 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
1274 break;
1275 case _PLL3_P:
1276 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
1277 break;
1278 case _PLL3_Q:
1279 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
1280 break;
1281 case _PLL3_R:
1282 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
1283 break;
1284 case _PLL4_P:
1285 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
1286 break;
1287 case _PLL4_Q:
1288 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
1289 break;
1290 case _PLL4_R:
1291 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
1292 break;
1293 /* Other */
1294 case _USB_PHY_48:
1295 clock = USB_PHY_48_MHZ;
1296 break;
1297 default:
1298 break;
1299 }
1300
1301 return clock;
1302 }
1303
__clk_enable(struct stm32mp1_clk_gate const * gate)1304 static void __clk_enable(struct stm32mp1_clk_gate const *gate)
1305 {
1306 uintptr_t rcc_base = stm32mp_rcc_base();
1307
1308 VERBOSE("Enable clock %u\n", gate->index);
1309
1310 if (gate->set_clr != 0U) {
1311 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
1312 } else {
1313 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
1314 }
1315
1316 /* Make sure the clock register has been written */
1317 (void)mmio_read_32(rcc_base + gate->offset);
1318 }
1319
__clk_disable(struct stm32mp1_clk_gate const * gate)1320 static void __clk_disable(struct stm32mp1_clk_gate const *gate)
1321 {
1322 uintptr_t rcc_base = stm32mp_rcc_base();
1323
1324 VERBOSE("Disable clock %u\n", gate->index);
1325
1326 dmbsy(); /* Ensure previous transactions are performed. */
1327
1328 if (gate->set_clr != 0U) {
1329 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
1330 BIT(gate->bit));
1331 } else {
1332 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
1333 }
1334
1335 /* Make sure the clock register has been written */
1336 (void)mmio_read_32(rcc_base + gate->offset);
1337 }
1338
__clk_is_enabled(struct stm32mp1_clk_gate const * gate)1339 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate)
1340 {
1341 uintptr_t rcc_base = stm32mp_rcc_base();
1342
1343 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
1344 }
1345
1346 /* Oscillators and PLLs are not gated at runtime */
clock_is_always_on(unsigned long id)1347 static bool clock_is_always_on(unsigned long id)
1348 {
1349 switch (id) {
1350 case CK_HSE:
1351 case CK_CSI:
1352 case CK_LSI:
1353 case CK_LSE:
1354 case CK_HSI:
1355 case CK_HSE_DIV2:
1356 case PLL1_Q:
1357 case PLL1_R:
1358 case PLL2_P:
1359 case PLL2_Q:
1360 case PLL2_R:
1361 case PLL3_P:
1362 case PLL3_Q:
1363 case PLL3_R:
1364 case CK_AXI:
1365 case CK_MPU:
1366 case CK_MCU:
1367 case RTC:
1368 case RTCAPB:
1369 return true;
1370 default:
1371 return false;
1372 }
1373 }
1374
__stm32mp1_clk_enable(unsigned long id,bool with_refcnt)1375 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt)
1376 {
1377 const struct stm32mp1_clk_gate *gate;
1378 int i;
1379
1380 if (clock_is_always_on(id)) {
1381 return;
1382 }
1383
1384 i = stm32mp1_clk_get_gated_id(id);
1385 if (i < 0) {
1386 ERROR("Clock %lu can't be enabled\n", id);
1387 panic();
1388 }
1389
1390 gate = gate_ref(i);
1391
1392 if (!with_refcnt) {
1393 __clk_enable(gate);
1394 return;
1395 }
1396
1397 #if defined(IMAGE_BL32)
1398 if (gate_is_non_secure(gate)) {
1399 /* Enable non-secure clock w/o any refcounting */
1400 __clk_enable(gate);
1401 return;
1402 }
1403 #endif
1404
1405 stm32mp1_clk_lock(&refcount_lock);
1406
1407 if (gate_refcounts[i] == 0U) {
1408 __clk_enable(gate);
1409 }
1410
1411 gate_refcounts[i]++;
1412 if (gate_refcounts[i] == UINT_MAX) {
1413 ERROR("Clock %lu refcount reached max value\n", id);
1414 panic();
1415 }
1416
1417 stm32mp1_clk_unlock(&refcount_lock);
1418 }
1419
__stm32mp1_clk_disable(unsigned long id,bool with_refcnt)1420 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt)
1421 {
1422 const struct stm32mp1_clk_gate *gate;
1423 int i;
1424
1425 if (clock_is_always_on(id)) {
1426 return;
1427 }
1428
1429 i = stm32mp1_clk_get_gated_id(id);
1430 if (i < 0) {
1431 ERROR("Clock %lu can't be disabled\n", id);
1432 panic();
1433 }
1434
1435 gate = gate_ref(i);
1436
1437 if (!with_refcnt) {
1438 __clk_disable(gate);
1439 return;
1440 }
1441
1442 #if defined(IMAGE_BL32)
1443 if (gate_is_non_secure(gate)) {
1444 /* Don't disable non-secure clocks */
1445 return;
1446 }
1447 #endif
1448
1449 stm32mp1_clk_lock(&refcount_lock);
1450
1451 if (gate_refcounts[i] == 0U) {
1452 ERROR("Clock %lu refcount reached 0\n", id);
1453 panic();
1454 }
1455 gate_refcounts[i]--;
1456
1457 if (gate_refcounts[i] == 0U) {
1458 __clk_disable(gate);
1459 }
1460
1461 stm32mp1_clk_unlock(&refcount_lock);
1462 }
1463
stm32mp_clk_enable(unsigned long id)1464 static int stm32mp_clk_enable(unsigned long id)
1465 {
1466 __stm32mp1_clk_enable(id, true);
1467
1468 return 0;
1469 }
1470
stm32mp_clk_disable(unsigned long id)1471 static void stm32mp_clk_disable(unsigned long id)
1472 {
1473 __stm32mp1_clk_disable(id, true);
1474 }
1475
stm32mp_clk_is_enabled(unsigned long id)1476 static bool stm32mp_clk_is_enabled(unsigned long id)
1477 {
1478 int i;
1479
1480 if (clock_is_always_on(id)) {
1481 return true;
1482 }
1483
1484 i = stm32mp1_clk_get_gated_id(id);
1485 if (i < 0) {
1486 panic();
1487 }
1488
1489 return __clk_is_enabled(gate_ref(i));
1490 }
1491
stm32mp_clk_get_rate(unsigned long id)1492 static unsigned long stm32mp_clk_get_rate(unsigned long id)
1493 {
1494 uintptr_t rcc_base = stm32mp_rcc_base();
1495 int p = stm32mp1_clk_get_parent(id);
1496 uint32_t prescaler, timpre;
1497 unsigned long parent_rate;
1498
1499 if (p < 0) {
1500 return 0;
1501 }
1502
1503 parent_rate = get_clock_rate(p);
1504
1505 switch (id) {
1506 case TIM2_K:
1507 case TIM3_K:
1508 case TIM4_K:
1509 case TIM5_K:
1510 case TIM6_K:
1511 case TIM7_K:
1512 case TIM12_K:
1513 case TIM13_K:
1514 case TIM14_K:
1515 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &
1516 RCC_APBXDIV_MASK;
1517 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &
1518 RCC_TIMGXPRER_TIMGXPRE;
1519 break;
1520
1521 case TIM1_K:
1522 case TIM8_K:
1523 case TIM15_K:
1524 case TIM16_K:
1525 case TIM17_K:
1526 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &
1527 RCC_APBXDIV_MASK;
1528 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &
1529 RCC_TIMGXPRER_TIMGXPRE;
1530 break;
1531
1532 default:
1533 return parent_rate;
1534 }
1535
1536 if (prescaler == 0U) {
1537 return parent_rate;
1538 }
1539
1540 return parent_rate * (timpre + 1U) * 2U;
1541 }
1542
stm32mp1_ls_osc_set(bool enable,uint32_t offset,uint32_t mask_on)1543 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
1544 {
1545 uintptr_t address = stm32mp_rcc_base() + offset;
1546
1547 if (enable) {
1548 mmio_setbits_32(address, mask_on);
1549 } else {
1550 mmio_clrbits_32(address, mask_on);
1551 }
1552 }
1553
stm32mp1_hs_ocs_set(bool enable,uint32_t mask_on)1554 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on)
1555 {
1556 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR;
1557 uintptr_t address = stm32mp_rcc_base() + offset;
1558
1559 mmio_write_32(address, mask_on);
1560 }
1561
stm32mp1_osc_wait(bool enable,uint32_t offset,uint32_t mask_rdy)1562 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy)
1563 {
1564 uint64_t timeout;
1565 uint32_t mask_test;
1566 uintptr_t address = stm32mp_rcc_base() + offset;
1567
1568 if (enable) {
1569 mask_test = mask_rdy;
1570 } else {
1571 mask_test = 0;
1572 }
1573
1574 timeout = timeout_init_us(OSCRDY_TIMEOUT);
1575 while ((mmio_read_32(address) & mask_rdy) != mask_test) {
1576 if (timeout_elapsed(timeout)) {
1577 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n",
1578 mask_rdy, address, enable, mmio_read_32(address));
1579 return -ETIMEDOUT;
1580 }
1581 }
1582
1583 return 0;
1584 }
1585
stm32mp1_lse_enable(bool bypass,bool digbyp,uint32_t lsedrv)1586 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv)
1587 {
1588 uint32_t value;
1589 uintptr_t rcc_base = stm32mp_rcc_base();
1590
1591 /* Do not reconfigure LSE if it is already ON */
1592 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) {
1593 return;
1594 }
1595
1596 if (digbyp) {
1597 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
1598 }
1599
1600 if (bypass || digbyp) {
1601 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
1602 }
1603
1604 /*
1605 * Warning: not recommended to switch directly from "high drive"
1606 * to "medium low drive", and vice-versa.
1607 */
1608 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
1609 RCC_BDCR_LSEDRV_SHIFT;
1610
1611 while (value != lsedrv) {
1612 if (value > lsedrv) {
1613 value--;
1614 } else {
1615 value++;
1616 }
1617
1618 mmio_clrsetbits_32(rcc_base + RCC_BDCR,
1619 RCC_BDCR_LSEDRV_MASK,
1620 value << RCC_BDCR_LSEDRV_SHIFT);
1621 }
1622
1623 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON);
1624 }
1625
stm32mp1_lse_wait(void)1626 static void stm32mp1_lse_wait(void)
1627 {
1628 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
1629 EARLY_ERROR("%s: failed\n", __func__);
1630 }
1631 }
1632
stm32mp1_lsi_set(bool enable)1633 static void stm32mp1_lsi_set(bool enable)
1634 {
1635 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
1636
1637 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
1638 EARLY_ERROR("%s: failed\n", __func__);
1639 }
1640 }
1641
stm32mp1_hse_enable(bool bypass,bool digbyp,bool css)1642 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css)
1643 {
1644 uintptr_t rcc_base = stm32mp_rcc_base();
1645
1646 if (digbyp) {
1647 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
1648 }
1649
1650 if (bypass || digbyp) {
1651 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1652 }
1653
1654 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
1655 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
1656 EARLY_ERROR("%s: failed\n", __func__);
1657 }
1658
1659 if (css) {
1660 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1661 }
1662
1663 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
1664 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) &&
1665 (!(digbyp || bypass))) {
1666 panic();
1667 }
1668 #endif
1669 }
1670
stm32mp1_csi_set(bool enable)1671 static void stm32mp1_csi_set(bool enable)
1672 {
1673 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
1674 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
1675 EARLY_ERROR("%s: failed\n", __func__);
1676 }
1677 }
1678
stm32mp1_hsi_set(bool enable)1679 static void stm32mp1_hsi_set(bool enable)
1680 {
1681 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
1682 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
1683 EARLY_ERROR("%s: failed\n", __func__);
1684 }
1685 }
1686
stm32mp1_set_hsidiv(uint8_t hsidiv)1687 static int stm32mp1_set_hsidiv(uint8_t hsidiv)
1688 {
1689 uint64_t timeout;
1690 uintptr_t rcc_base = stm32mp_rcc_base();
1691 uintptr_t address = rcc_base + RCC_OCRDYR;
1692
1693 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
1694 RCC_HSICFGR_HSIDIV_MASK,
1695 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
1696
1697 timeout = timeout_init_us(HSIDIV_TIMEOUT);
1698 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
1699 if (timeout_elapsed(timeout)) {
1700 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
1701 address, mmio_read_32(address));
1702 return -ETIMEDOUT;
1703 }
1704 }
1705
1706 return 0;
1707 }
1708
stm32mp1_hsidiv(unsigned long hsifreq)1709 static int stm32mp1_hsidiv(unsigned long hsifreq)
1710 {
1711 uint8_t hsidiv;
1712 uint32_t hsidivfreq = MAX_HSI_HZ;
1713
1714 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1715 if (hsidivfreq == hsifreq) {
1716 break;
1717 }
1718
1719 hsidivfreq /= 2U;
1720 }
1721
1722 if (hsidiv == 4U) {
1723 EARLY_ERROR("Invalid clk-hsi frequency\n");
1724 return -1;
1725 }
1726
1727 if (hsidiv != 0U) {
1728 return stm32mp1_set_hsidiv(hsidiv);
1729 }
1730
1731 return 0;
1732 }
1733
stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,unsigned int clksrc,uint32_t * pllcfg,uint32_t fracv)1734 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
1735 unsigned int clksrc,
1736 uint32_t *pllcfg, uint32_t fracv)
1737 {
1738 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1739 uintptr_t rcc_base = stm32mp_rcc_base();
1740 uintptr_t pllxcr = rcc_base + pll->pllxcr;
1741 enum stm32mp1_plltype type = pll->plltype;
1742 uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
1743 unsigned long refclk;
1744 uint32_t ifrge = 0U;
1745 uint32_t src, value;
1746
1747 /* Check PLL output */
1748 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
1749 return false;
1750 }
1751
1752 /* Check current clksrc */
1753 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK;
1754 if (src != (clksrc & RCC_SELR_SRC_MASK)) {
1755 return false;
1756 }
1757
1758 /* Check Div */
1759 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
1760
1761 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1762 (pllcfg[PLLCFG_M] + 1U);
1763
1764 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1765 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1766 return false;
1767 }
1768
1769 if ((type == PLL_800) && (refclk >= 8000000U)) {
1770 ifrge = 1U;
1771 }
1772
1773 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1774 RCC_PLLNCFGR1_DIVN_MASK;
1775 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1776 RCC_PLLNCFGR1_DIVM_MASK;
1777 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1778 RCC_PLLNCFGR1_IFRGE_MASK;
1779 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
1780 return false;
1781 }
1782
1783 /* Fractional configuration */
1784 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1785 value |= RCC_PLLNFRACR_FRACLE;
1786 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
1787 return false;
1788 }
1789
1790 /* Output config */
1791 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1792 RCC_PLLNCFGR2_DIVP_MASK;
1793 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1794 RCC_PLLNCFGR2_DIVQ_MASK;
1795 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1796 RCC_PLLNCFGR2_DIVR_MASK;
1797 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
1798 return false;
1799 }
1800
1801 return true;
1802 }
1803
stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)1804 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)
1805 {
1806 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1807 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1808
1809 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1810 mmio_clrsetbits_32(pllxcr,
1811 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1812 RCC_PLLNCR_DIVREN,
1813 RCC_PLLNCR_PLLON);
1814 }
1815
stm32mp1_pll_output(enum stm32mp1_pll_id pll_id,uint32_t output)1816 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
1817 {
1818 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1819 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1820 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1821
1822 /* Wait PLL lock */
1823 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
1824 if (timeout_elapsed(timeout)) {
1825 EARLY_ERROR("PLL%u start failed @ 0x%lx: 0x%x\n",
1826 pll_id, pllxcr, mmio_read_32(pllxcr));
1827 return -ETIMEDOUT;
1828 }
1829 }
1830
1831 /* Start the requested output */
1832 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1833
1834 return 0;
1835 }
1836
stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)1837 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)
1838 {
1839 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1840 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1841 uint64_t timeout;
1842
1843 /* Stop all output */
1844 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1845 RCC_PLLNCR_DIVREN);
1846
1847 /* Stop PLL */
1848 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
1849
1850 timeout = timeout_init_us(PLLRDY_TIMEOUT);
1851 /* Wait PLL stopped */
1852 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
1853 if (timeout_elapsed(timeout)) {
1854 EARLY_ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n",
1855 pll_id, pllxcr, mmio_read_32(pllxcr));
1856 return -ETIMEDOUT;
1857 }
1858 }
1859
1860 return 0;
1861 }
1862
stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,uint32_t * pllcfg)1863 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,
1864 uint32_t *pllcfg)
1865 {
1866 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1867 uintptr_t rcc_base = stm32mp_rcc_base();
1868 uint32_t value;
1869
1870 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1871 RCC_PLLNCFGR2_DIVP_MASK;
1872 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1873 RCC_PLLNCFGR2_DIVQ_MASK;
1874 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1875 RCC_PLLNCFGR2_DIVR_MASK;
1876 mmio_write_32(rcc_base + pll->pllxcfgr2, value);
1877 }
1878
stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,uint32_t * pllcfg,uint32_t fracv)1879 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,
1880 uint32_t *pllcfg, uint32_t fracv)
1881 {
1882 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1883 uintptr_t rcc_base = stm32mp_rcc_base();
1884 enum stm32mp1_plltype type = pll->plltype;
1885 unsigned long refclk;
1886 uint32_t ifrge = 0;
1887 uint32_t src, value;
1888
1889 src = mmio_read_32(rcc_base + pll->rckxselr) &
1890 RCC_SELR_REFCLK_SRC_MASK;
1891
1892 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1893 (pllcfg[PLLCFG_M] + 1U);
1894
1895 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1896 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1897 return -EINVAL;
1898 }
1899
1900 if ((type == PLL_800) && (refclk >= 8000000U)) {
1901 ifrge = 1U;
1902 }
1903
1904 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1905 RCC_PLLNCFGR1_DIVN_MASK;
1906 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1907 RCC_PLLNCFGR1_DIVM_MASK;
1908 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1909 RCC_PLLNCFGR1_IFRGE_MASK;
1910 mmio_write_32(rcc_base + pll->pllxcfgr1, value);
1911
1912 /* Fractional configuration */
1913 value = 0;
1914 mmio_write_32(rcc_base + pll->pllxfracr, value);
1915
1916 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1917 mmio_write_32(rcc_base + pll->pllxfracr, value);
1918
1919 value |= RCC_PLLNFRACR_FRACLE;
1920 mmio_write_32(rcc_base + pll->pllxfracr, value);
1921
1922 stm32mp1_pll_config_output(pll_id, pllcfg);
1923
1924 return 0;
1925 }
1926
stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id,uint32_t * csg)1927 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg)
1928 {
1929 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1930 uint32_t pllxcsg = 0;
1931
1932 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1933 RCC_PLLNCSGR_MOD_PER_MASK;
1934
1935 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1936 RCC_PLLNCSGR_INC_STEP_MASK;
1937
1938 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1939 RCC_PLLNCSGR_SSCG_MODE_MASK;
1940
1941 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
1942
1943 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr,
1944 RCC_PLLNCR_SSCG_CTRL);
1945 }
1946
clk_compute_pll1_settings(unsigned long input_freq,uint32_t freq_khz,uint32_t * pllcfg,uint32_t * fracv)1947 static int clk_compute_pll1_settings(unsigned long input_freq,
1948 uint32_t freq_khz,
1949 uint32_t *pllcfg, uint32_t *fracv)
1950 {
1951 unsigned long long best_diff = ULLONG_MAX;
1952 unsigned int divm;
1953
1954 /* Following parameters have always the same value */
1955 pllcfg[PLLCFG_Q] = 0U;
1956 pllcfg[PLLCFG_R] = 0U;
1957 pllcfg[PLLCFG_O] = PQR(1, 0, 0);
1958
1959 for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) {
1960 unsigned long post_divm = input_freq / divm;
1961 unsigned int divp;
1962
1963 if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) {
1964 continue;
1965 }
1966
1967 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
1968 unsigned long long output_freq = freq_khz * 1000ULL;
1969 unsigned long long freq;
1970 unsigned long long divn;
1971 unsigned long long frac;
1972 unsigned int i;
1973
1974 freq = output_freq * divm * (divp + 1U);
1975
1976 divn = (freq / input_freq) - 1U;
1977 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) {
1978 continue;
1979 }
1980
1981 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX);
1982
1983 /* 2 loops to refine the fractional part */
1984 for (i = 2U; i != 0U; i--) {
1985 unsigned long long diff;
1986 unsigned long long vco;
1987
1988 if (frac > FRAC_MAX) {
1989 break;
1990 }
1991
1992 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX);
1993
1994 if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) {
1995 frac++;
1996 continue;
1997 }
1998
1999 freq = vco / (divp + 1U);
2000 if (output_freq < freq) {
2001 diff = freq - output_freq;
2002 } else {
2003 diff = output_freq - freq;
2004 }
2005
2006 if (diff < best_diff) {
2007 pllcfg[PLLCFG_M] = divm - 1U;
2008 pllcfg[PLLCFG_N] = (uint32_t)divn;
2009 pllcfg[PLLCFG_P] = divp;
2010 *fracv = (uint32_t)frac;
2011
2012 if (diff == 0U) {
2013 return 0;
2014 }
2015
2016 best_diff = diff;
2017 }
2018
2019 frac++;
2020 }
2021 }
2022 }
2023
2024 if (best_diff == ULLONG_MAX) {
2025 return -EINVAL;
2026 }
2027
2028 return 0;
2029 }
2030
clk_get_pll1_settings(uint32_t clksrc,uint32_t freq_khz,uint32_t * pllcfg,uint32_t * fracv)2031 static int clk_get_pll1_settings(uint32_t clksrc, uint32_t freq_khz,
2032 uint32_t *pllcfg, uint32_t *fracv)
2033 {
2034 unsigned long input_freq = 0UL;
2035
2036 assert(pllcfg != NULL);
2037 assert(fracv != NULL);
2038
2039 switch (clksrc) {
2040 case CLK_PLL12_HSI:
2041 input_freq = stm32mp_clk_get_rate(CK_HSI);
2042 break;
2043 case CLK_PLL12_HSE:
2044 input_freq = stm32mp_clk_get_rate(CK_HSE);
2045 break;
2046 default:
2047 break;
2048 }
2049
2050 if (input_freq == 0UL) {
2051 panic();
2052 }
2053
2054 return clk_compute_pll1_settings(input_freq, freq_khz, pllcfg, fracv);
2055 }
2056
stm32_clk_dividers_configure(struct stm32_clk_priv * priv)2057 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv)
2058 {
2059 struct stm32_clk_platdata *pdata = priv->pdata;
2060 uint32_t i;
2061
2062 for (i = 0U; i < pdata->nclkdiv; i++) {
2063 uint32_t div_id, div_n;
2064 uint32_t val;
2065 int ret;
2066
2067 val = pdata->clkdiv[i] & CMD_DATA_MASK;
2068 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT;
2069 div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
2070
2071 ret = clk_stm32_set_div(priv, div_id, div_n);
2072 if (ret != 0) {
2073 return ret;
2074 }
2075 }
2076
2077 return 0;
2078 }
2079
stm32_clk_configure_clk(struct stm32_clk_priv * priv,uint32_t data)2080 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
2081 {
2082 uint32_t sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT;
2083 uint32_t enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT;
2084 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT;
2085 struct stm32_clk_platdata *pdata = priv->pdata;
2086
2087 if (binding_id == RTC) {
2088 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
2089
2090 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || (enable != 0U)) {
2091 mmio_clrsetbits_32(address, RCC_BDCR_RTCSRC_MASK,
2092 (sel & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);
2093
2094 mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
2095 /* Configure LSE CSS */
2096 if (pdata->lse_css) {
2097 mmio_setbits_32(priv->base + RCC_BDCR, RCC_BDCR_LSECSSON);
2098 }
2099 }
2100 }
2101
2102 return 0;
2103 }
2104
stm32_clk_configure_by_addr_val(struct stm32_clk_priv * priv,uint32_t data)2105 static int stm32_clk_configure_by_addr_val(struct stm32_clk_priv *priv,
2106 uint32_t data)
2107 {
2108 uint32_t addr = data >> CLK_ADDR_SHIFT;
2109 uint32_t val = data & CLK_ADDR_VAL_MASK;
2110
2111 mmio_setbits_32(priv->base + addr, val);
2112
2113 return 0;
2114 }
2115
stm32_clk_source_configure(struct stm32_clk_priv * priv)2116 static int stm32_clk_source_configure(struct stm32_clk_priv *priv)
2117 {
2118 struct stm32_clk_platdata *pdata = priv->pdata;
2119 bool ckper_disabled = false;
2120 uint32_t i;
2121
2122 for (i = 0U; i < pdata->nclksrc; i++) {
2123 uint32_t val = pdata->clksrc[i];
2124 uint32_t cmd, cmd_data;
2125 int ret;
2126
2127 if (val & CMD_ADDR_BIT) {
2128 ret = stm32_clk_configure_by_addr_val(priv, val & ~CMD_ADDR_BIT);
2129 if (ret != 0) {
2130 return ret;
2131 }
2132
2133 continue;
2134 }
2135
2136 if (val == (uint32_t)CLK_CKPER_DISABLED) {
2137 ckper_disabled = true;
2138 continue;
2139 }
2140
2141 cmd = (val & CMD_MASK) >> CMD_SHIFT;
2142 cmd_data = val & ~CMD_MASK;
2143
2144 switch (cmd) {
2145 case CMD_MUX:
2146 ret = stm32_clk_configure_mux(priv, cmd_data);
2147 break;
2148
2149 case CMD_CLK:
2150 ret = stm32_clk_configure_clk(priv, cmd_data);
2151 break;
2152 default:
2153 ret = -EINVAL;
2154 break;
2155 }
2156
2157 if (ret != 0) {
2158 return ret;
2159 }
2160 }
2161
2162 /*
2163 * CKPER is source for some peripheral clocks
2164 * (FMC-NAND / QPSI-NOR) and switching source is allowed
2165 * only if previous clock is still ON
2166 * => deactivate CKPER only after switching clock
2167 */
2168 if (!ckper_disabled) {
2169 return 0;
2170 }
2171
2172 return stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);
2173 }
2174
stm32mp1_pll_configure_src(struct stm32_clk_priv * priv,int pll_idx)2175 static int stm32mp1_pll_configure_src(struct stm32_clk_priv *priv, int pll_idx)
2176 {
2177 struct stm32_clk_platdata *pdata = priv->pdata;
2178 struct stm32_pll_dt_cfg *pll_conf = &pdata->pll[pll_idx];
2179
2180 if (!pll_conf->status) {
2181 return 0;
2182 }
2183
2184 return stm32_clk_configure_mux(priv, pll_conf->src);
2185 }
2186
stm32mp1_clk_init(void)2187 int stm32mp1_clk_init(void)
2188 {
2189 struct stm32_clk_priv *priv = clk_stm32_get_priv();
2190 struct stm32_clk_platdata *pdata = priv->pdata;
2191 struct stm32_pll_dt_cfg *pll_conf = pdata->pll;
2192 int ret;
2193 enum stm32mp1_pll_id i;
2194 bool pll3_preserve = false;
2195 bool pll4_preserve = false;
2196 bool pll4_bootrom = false;
2197 int stgen_p = stm32mp1_clk_get_parent(STGEN_K);
2198 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K);
2199 uint32_t usbreg_bootrom = 0U;
2200
2201 if (!pll_conf[_PLL1].status) {
2202 ret = clk_get_pll1_settings(pll_conf[_PLL2].src, PLL1_NOMINAL_FREQ_IN_KHZ,
2203 pll_conf[_PLL1].cfg, &pll_conf[_PLL1].frac);
2204 if (ret != 0) {
2205 return ret;
2206 }
2207
2208 pll_conf[_PLL1].status = true;
2209 pll_conf[_PLL1].src = pll_conf[_PLL2].src;
2210 }
2211
2212 /*
2213 * Switch ON oscillator found in device-tree.
2214 * Note: HSI already ON after BootROM stage.
2215 */
2216 if (stm32mp1_osc[_LSI] != 0U) {
2217 stm32mp1_lsi_set(true);
2218 }
2219 if (stm32mp1_osc[_LSE] != 0U) {
2220 const char *name = stm32mp_osc_node_label[_LSE];
2221 bool bypass, digbyp;
2222 uint32_t lsedrv;
2223
2224 bypass = fdt_clk_read_bool(name, "st,bypass");
2225 digbyp = fdt_clk_read_bool(name, "st,digbypass");
2226 pdata->lse_css = fdt_clk_read_bool(name, "st,css");
2227 lsedrv = fdt_clk_read_uint32_default(name, "st,drive",
2228 LSEDRV_MEDIUM_HIGH);
2229 stm32mp1_lse_enable(bypass, digbyp, lsedrv);
2230 }
2231 if (stm32mp1_osc[_HSE] != 0U) {
2232 const char *name = stm32mp_osc_node_label[_HSE];
2233 bool bypass, digbyp, css;
2234
2235 bypass = fdt_clk_read_bool(name, "st,bypass");
2236 digbyp = fdt_clk_read_bool(name, "st,digbypass");
2237 css = fdt_clk_read_bool(name, "st,css");
2238 stm32mp1_hse_enable(bypass, digbyp, css);
2239 }
2240 /*
2241 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
2242 * => switch on CSI even if node is not present in device tree
2243 */
2244 stm32mp1_csi_set(true);
2245
2246 /* Come back to HSI */
2247 ret = stm32_clk_configure_mux(priv, CLK_MPU_HSI);
2248 if (ret != 0) {
2249 return ret;
2250 }
2251 ret = stm32_clk_configure_mux(priv, CLK_AXI_HSI);
2252 if (ret != 0) {
2253 return ret;
2254 }
2255 ret = stm32_clk_configure_mux(priv, CLK_MCU_HSI);
2256 if (ret != 0) {
2257 return ret;
2258 }
2259 if ((mmio_read_32(priv->base + RCC_MP_RSTSCLRR) &
2260 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
2261 pll3_preserve = stm32mp1_check_pll_conf(_PLL3,
2262 pll_conf[_PLL3].src,
2263 pll_conf[_PLL3].cfg,
2264 pll_conf[_PLL3].frac);
2265 pll4_preserve = stm32mp1_check_pll_conf(_PLL4,
2266 pll_conf[_PLL4].src,
2267 pll_conf[_PLL4].cfg,
2268 pll_conf[_PLL4].frac);
2269 }
2270 /* Don't initialize PLL4, when used by BOOTROM */
2271 if ((stm32mp_get_boot_itf_selected() ==
2272 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) &&
2273 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) {
2274 pll4_bootrom = true;
2275 pll4_preserve = true;
2276 }
2277
2278 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
2279 if (((i == _PLL3) && pll3_preserve) ||
2280 ((i == _PLL4) && pll4_preserve)) {
2281 continue;
2282 }
2283
2284 ret = stm32mp1_pll_stop(i);
2285 if (ret != 0) {
2286 return ret;
2287 }
2288 }
2289
2290 /* Configure HSIDIV */
2291 if (stm32mp1_osc[_HSI] != 0U) {
2292 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
2293 if (ret != 0) {
2294 return ret;
2295 }
2296
2297 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
2298 }
2299
2300 /* Configure dividers */
2301 ret = stm32_clk_dividers_configure(priv);
2302 if (ret != 0) {
2303 return ret;
2304 }
2305
2306 /* Configure PLLs source */
2307 ret = stm32mp1_pll_configure_src(priv, _PLL1);
2308 if (ret != 0) {
2309 return ret;
2310 }
2311
2312 if (!pll3_preserve) {
2313 ret = stm32mp1_pll_configure_src(priv, _PLL3);
2314 if (ret != 0) {
2315 return ret;
2316 }
2317 }
2318
2319 if (!pll4_preserve) {
2320 ret = stm32mp1_pll_configure_src(priv, _PLL4);
2321 if (ret != 0) {
2322 return ret;
2323 }
2324 }
2325
2326 /* Configure and start PLLs */
2327 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
2328 if (((i == _PLL3) && pll3_preserve) ||
2329 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
2330 continue;
2331 }
2332
2333 if (!pll_conf[i].status) {
2334 continue;
2335 }
2336
2337 if ((i == _PLL4) && pll4_bootrom) {
2338 /* Set output divider if not done by the Bootrom */
2339 stm32mp1_pll_config_output(i, pll_conf[i].cfg);
2340 continue;
2341 }
2342
2343 ret = stm32mp1_pll_config(i, pll_conf[i].cfg, pll_conf[i].frac);
2344 if (ret != 0) {
2345 return ret;
2346 }
2347
2348 if (pll_conf[i].csg_enabled) {
2349 stm32mp1_pll_csg(i, pll_conf[i].csg);
2350 }
2351
2352 stm32mp1_pll_start(i);
2353 }
2354 /* Wait and start PLLs output when ready */
2355 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
2356 if (!pll_conf[i].status) {
2357 continue;
2358 }
2359
2360 ret = stm32mp1_pll_output(i, pll_conf[i].cfg[PLLCFG_O]);
2361 if (ret != 0) {
2362 return ret;
2363 }
2364 }
2365 /* Wait LSE ready before to use it */
2366 if (stm32mp1_osc[_LSE] != 0U) {
2367 stm32mp1_lse_wait();
2368 }
2369
2370 if (pll4_bootrom) {
2371 usbreg_bootrom = mmio_read_32(priv->base + RCC_USBCKSELR);
2372 }
2373
2374 /* Configure with expected clock source */
2375 ret = stm32_clk_source_configure(priv);
2376 if (ret != 0) {
2377 panic();
2378 }
2379
2380 if (pll4_bootrom) {
2381 uint32_t usbreg_value, usbreg_mask;
2382 const struct stm32mp1_clk_sel *sel;
2383
2384 sel = clk_sel_ref(_USBPHY_SEL);
2385 usbreg_mask = (uint32_t)sel->msk << sel->src;
2386 sel = clk_sel_ref(_USBO_SEL);
2387 usbreg_mask |= (uint32_t)sel->msk << sel->src;
2388
2389 usbreg_value = mmio_read_32(priv->base + RCC_USBCKSELR) &
2390 usbreg_mask;
2391 usbreg_bootrom &= usbreg_mask;
2392 if (usbreg_bootrom != usbreg_value) {
2393 EARLY_ERROR("forbidden new USB clk path\n");
2394 EARLY_ERROR("vs bootrom on USB boot\n");
2395 return -FDT_ERR_BADVALUE;
2396 }
2397 }
2398
2399 /* Switch OFF HSI if not found in device-tree */
2400 if (stm32mp1_osc[_HSI] == 0U) {
2401 stm32mp1_hsi_set(false);
2402 }
2403
2404 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K));
2405
2406 /* Software Self-Refresh mode (SSR) during DDR initilialization */
2407 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR,
2408 RCC_DDRITFCR_DDRCKMOD_MASK,
2409 RCC_DDRITFCR_DDRCKMOD_SSR <<
2410 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2411
2412 return 0;
2413 }
2414
stm32mp1_osc_clk_init(const char * name,enum stm32mp_osc_id index)2415 static void stm32mp1_osc_clk_init(const char *name,
2416 enum stm32mp_osc_id index)
2417 {
2418 uint32_t frequency;
2419
2420 if (fdt_osc_read_freq(name, &frequency) == 0) {
2421 stm32mp1_osc[index] = frequency;
2422 }
2423 }
2424
stm32mp1_osc_init(void)2425 static void stm32mp1_osc_init(void)
2426 {
2427 enum stm32mp_osc_id i;
2428
2429 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
2430 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i);
2431 }
2432 }
2433
2434 #ifdef STM32MP_SHARED_RESOURCES
2435 /*
2436 * Get the parent ID of the target parent clock, for tagging as secure
2437 * shared clock dependencies.
2438 */
get_parent_id_parent(unsigned int parent_id)2439 static int get_parent_id_parent(unsigned int parent_id)
2440 {
2441 enum stm32mp1_parent_sel s = _UNKNOWN_SEL;
2442 enum stm32mp1_pll_id pll_id;
2443 uint32_t p_sel;
2444 uintptr_t rcc_base = stm32mp_rcc_base();
2445
2446 switch (parent_id) {
2447 case _ACLK:
2448 case _PCLK4:
2449 case _PCLK5:
2450 s = _AXIS_SEL;
2451 break;
2452 case _PLL1_P:
2453 case _PLL1_Q:
2454 case _PLL1_R:
2455 pll_id = _PLL1;
2456 break;
2457 case _PLL2_P:
2458 case _PLL2_Q:
2459 case _PLL2_R:
2460 pll_id = _PLL2;
2461 break;
2462 case _PLL3_P:
2463 case _PLL3_Q:
2464 case _PLL3_R:
2465 pll_id = _PLL3;
2466 break;
2467 case _PLL4_P:
2468 case _PLL4_Q:
2469 case _PLL4_R:
2470 pll_id = _PLL4;
2471 break;
2472 case _PCLK1:
2473 case _PCLK2:
2474 case _HCLK2:
2475 case _HCLK6:
2476 case _CK_PER:
2477 case _CK_MPU:
2478 case _CK_MCU:
2479 case _USB_PHY_48:
2480 /* We do not expect to access these */
2481 panic();
2482 break;
2483 default:
2484 /* Other parents have no parent */
2485 return -1;
2486 }
2487
2488 if (s != _UNKNOWN_SEL) {
2489 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s);
2490
2491 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &
2492 sel->msk;
2493
2494 if (p_sel < sel->nb_parent) {
2495 return (int)sel->parent[p_sel];
2496 }
2497 } else {
2498 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
2499
2500 p_sel = mmio_read_32(rcc_base + pll->rckxselr) &
2501 RCC_SELR_REFCLK_SRC_MASK;
2502
2503 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) {
2504 return (int)pll->refclk[p_sel];
2505 }
2506 }
2507
2508 VERBOSE("No parent selected for %s\n",
2509 stm32mp1_clk_parent_name[parent_id]);
2510
2511 return -1;
2512 }
2513
secure_parent_clocks(unsigned long parent_id)2514 static void secure_parent_clocks(unsigned long parent_id)
2515 {
2516 int grandparent_id;
2517
2518 switch (parent_id) {
2519 case _PLL3_P:
2520 case _PLL3_Q:
2521 case _PLL3_R:
2522 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2523 break;
2524
2525 /* These clocks are always secure when RCC is secure */
2526 case _ACLK:
2527 case _HCLK2:
2528 case _HCLK6:
2529 case _PCLK4:
2530 case _PCLK5:
2531 case _PLL1_P:
2532 case _PLL1_Q:
2533 case _PLL1_R:
2534 case _PLL2_P:
2535 case _PLL2_Q:
2536 case _PLL2_R:
2537 case _HSI:
2538 case _HSI_KER:
2539 case _LSI:
2540 case _CSI:
2541 case _CSI_KER:
2542 case _HSE:
2543 case _HSE_KER:
2544 case _HSE_KER_DIV2:
2545 case _HSE_RTC:
2546 case _LSE:
2547 break;
2548
2549 default:
2550 VERBOSE("Cannot secure parent clock %s\n",
2551 stm32mp1_clk_parent_name[parent_id]);
2552 panic();
2553 }
2554
2555 grandparent_id = get_parent_id_parent(parent_id);
2556 if (grandparent_id >= 0) {
2557 secure_parent_clocks(grandparent_id);
2558 }
2559 }
2560
stm32mp1_register_clock_parents_secure(unsigned long clock_id)2561 void stm32mp1_register_clock_parents_secure(unsigned long clock_id)
2562 {
2563 int parent_id;
2564
2565 if (!stm32mp1_rcc_is_secure()) {
2566 return;
2567 }
2568
2569 switch (clock_id) {
2570 case PLL1:
2571 case PLL2:
2572 /* PLL1/PLL2 are always secure: nothing to do */
2573 break;
2574 case PLL3:
2575 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
2576 break;
2577 case PLL4:
2578 ERROR("PLL4 cannot be secured\n");
2579 panic();
2580 break;
2581 default:
2582 /* Others are expected gateable clock */
2583 parent_id = stm32mp1_clk_get_parent(clock_id);
2584 if (parent_id < 0) {
2585 INFO("No parent found for clock %lu\n", clock_id);
2586 } else {
2587 secure_parent_clocks(parent_id);
2588 }
2589 break;
2590 }
2591 }
2592 #endif /* STM32MP_SHARED_RESOURCES */
2593
stm32mp1_clk_mcuss_protect(bool enable)2594 void stm32mp1_clk_mcuss_protect(bool enable)
2595 {
2596 uintptr_t rcc_base = stm32mp_rcc_base();
2597
2598 if (enable) {
2599 mmio_setbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
2600 } else {
2601 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
2602 }
2603 }
2604
sync_earlyboot_clocks_state(void)2605 static void sync_earlyboot_clocks_state(void)
2606 {
2607 unsigned int idx;
2608 const unsigned long secure_enable[] = {
2609 AXIDCG,
2610 BSEC,
2611 DDRC1, DDRC1LP,
2612 DDRC2, DDRC2LP,
2613 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP,
2614 DDRPHYC, DDRPHYCLP,
2615 RTCAPB,
2616 TZC1, TZC2,
2617 TZPC,
2618 STGEN_K,
2619 };
2620
2621 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) {
2622 stm32mp_clk_enable(secure_enable[idx]);
2623 }
2624 }
2625
2626 static const struct clk_ops stm32mp_clk_ops = {
2627 .enable = stm32mp_clk_enable,
2628 .disable = stm32mp_clk_disable,
2629 .is_enabled = stm32mp_clk_is_enabled,
2630 .get_rate = stm32mp_clk_get_rate,
2631 .get_parent = stm32mp1_clk_get_parent,
2632 };
2633
2634 struct stm32_pll_dt_cfg mp15_pll[_PLL_NB];
2635 uint32_t mp15_clksrc[MUX_NB];
2636 uint32_t mp15_clkdiv[DIV_NB];
2637
2638 struct stm32_clk_platdata stm32mp15_clock_pdata = {
2639 .pll = mp15_pll,
2640 .npll = _PLL_NB,
2641 .clksrc = mp15_clksrc,
2642 .nclksrc = MUX_NB,
2643 .clkdiv = mp15_clkdiv,
2644 .nclkdiv = DIV_NB,
2645 };
2646
2647 static struct stm32_clk_priv stm32mp15_clock_data = {
2648 .base = RCC_BASE,
2649 .parents = parent_mp15,
2650 .nb_parents = ARRAY_SIZE(parent_mp15),
2651 .div = dividers_mp15,
2652 .nb_div = ARRAY_SIZE(dividers_mp15),
2653 .pdata = &stm32mp15_clock_pdata,
2654 };
2655
stm32_clk_parse_fdt_by_name(void * fdt,int node,const char * name,uint32_t * tab,uint32_t * nb)2656 static int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name,
2657 uint32_t *tab, uint32_t *nb)
2658 {
2659 const fdt32_t *cell;
2660 int len = 0;
2661 uint32_t i;
2662
2663 cell = fdt_getprop(fdt, node, name, &len);
2664 if (cell == NULL) {
2665 *nb = 0U;
2666 return 0;
2667 }
2668
2669 for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) {
2670 tab[i] = fdt32_to_cpu(cell[i]);
2671 }
2672
2673 *nb = (uint32_t)len / sizeof(uint32_t);
2674
2675 return 0;
2676 }
2677
2678 #define RCC_PLL_NAME_SIZE 12
2679
clk_stm32_load_vco_config(void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)2680 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2681 {
2682 int err;
2683
2684 err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, &pll->cfg[PLLCFG_M]);
2685 if (err != 0) {
2686 return err;
2687 }
2688
2689 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLLCSG_NB, pll->csg);
2690 if (err == 0) {
2691 pll->csg_enabled = true;
2692 } else if (err == -FDT_ERR_NOTFOUND) {
2693 pll->csg_enabled = false;
2694 } else {
2695 return err;
2696 }
2697
2698 pll->status = true;
2699
2700 pll->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);
2701
2702 pll->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);
2703
2704 return 0;
2705 }
2706
clk_stm32_load_output_config(void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)2707 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2708 {
2709 int err;
2710
2711 err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB,
2712 &pll->cfg[PLLCFG_P]);
2713 if (err != 0) {
2714 return err;
2715 }
2716
2717 pll->cfg[PLLCFG_O] = PQR(1, 1, 1);
2718
2719 return 0;
2720 }
2721
clk_stm32_parse_pll_fdt(void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)2722 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2723 {
2724 const fdt32_t *cuint;
2725 int subnode_pll;
2726 int subnode_vco;
2727 int err;
2728
2729 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
2730 if (cuint == NULL) {
2731 /* Case of no pll is defined */
2732 return 0;
2733 }
2734
2735 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
2736 if (subnode_pll < 0) {
2737 return -FDT_ERR_NOTFOUND;
2738 }
2739
2740 cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL);
2741 if (cuint == NULL) {
2742 return -FDT_ERR_NOTFOUND;
2743 }
2744
2745 subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
2746 if (subnode_vco < 0) {
2747 return -FDT_ERR_NOTFOUND;
2748 }
2749
2750 err = clk_stm32_load_vco_config(fdt, subnode_vco, pll);
2751 if (err != 0) {
2752 return err;
2753 }
2754
2755 err = clk_stm32_load_output_config(fdt, subnode_pll, pll);
2756 if (err != 0) {
2757 return err;
2758 }
2759
2760 return 0;
2761 }
2762
stm32_clk_parse_fdt_all_pll(void * fdt,int node,struct stm32_clk_platdata * pdata)2763 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata)
2764 {
2765 size_t i = 0U;
2766
2767 for (i = _PLL1; i < pdata->npll; i++) {
2768 struct stm32_pll_dt_cfg *pll = pdata->pll + i;
2769 char name[RCC_PLL_NAME_SIZE];
2770 int subnode;
2771 int err;
2772
2773 snprintf(name, sizeof(name), "st,pll@%u", i);
2774
2775 subnode = fdt_subnode_offset(fdt, node, name);
2776 if ((subnode < 0) || !fdt_check_node(subnode)) {
2777 continue;
2778 }
2779
2780 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);
2781 if (err != 0) {
2782 panic();
2783 }
2784 }
2785
2786 return 0;
2787 }
2788
stm32_clk_parse_fdt(struct stm32_clk_platdata * pdata)2789 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata)
2790 {
2791 void *fdt = NULL;
2792 int node;
2793 uint32_t err;
2794
2795 if (fdt_get_address(&fdt) == 0) {
2796 return -ENOENT;
2797 }
2798
2799 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
2800 if (node < 0) {
2801 panic();
2802 }
2803
2804 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
2805 if (err != 0) {
2806 return err;
2807 }
2808
2809 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv);
2810 if (err != 0) {
2811 return err;
2812 }
2813
2814 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc);
2815 if (err != 0) {
2816 return err;
2817 }
2818
2819 return 0;
2820 }
2821
stm32mp1_clk_probe(void)2822 int stm32mp1_clk_probe(void)
2823 {
2824 uintptr_t base = RCC_BASE;
2825 int ret;
2826
2827 #if defined(IMAGE_BL32)
2828 if (!fdt_get_rcc_secure_state()) {
2829 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U);
2830 }
2831 #endif
2832
2833 stm32mp1_osc_init();
2834
2835 ret = stm32_clk_parse_fdt(&stm32mp15_clock_pdata);
2836 if (ret != 0) {
2837 return ret;
2838 }
2839
2840 ret = clk_stm32_init(&stm32mp15_clock_data, base);
2841 if (ret != 0) {
2842 return ret;
2843 }
2844
2845 sync_earlyboot_clocks_state();
2846
2847 clk_register(&stm32mp_clk_ops);
2848
2849 return 0;
2850 }
2851