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Searched refs:ARM_NS_DRAM1_BASE (Results 1 – 17 of 17) sorted by relevance

/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_drtm_addr.c23 } else if ((region_start >= ARM_NS_DRAM1_BASE) && in plat_drtm_validate_ns_region()
24 (region_start < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)) && in plat_drtm_validate_ns_region()
25 (region_end >= ARM_NS_DRAM1_BASE) && in plat_drtm_validate_ns_region()
26 (region_end < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { in plat_drtm_validate_ns_region()
/rk3399_ARM-atf/plat/nuvoton/common/
H A Dnuvoton_pm.c33 if ((entrypoint >= ARM_NS_DRAM1_BASE) && in arm_validate_ns_entrypoint()
34 (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { in arm_validate_ns_entrypoint()
/rk3399_ARM-atf/plat/arm/board/corstone1000/common/
H A Dcorstone1000_pm.c51 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { in corstone1000_validate_ns_entrypoint()
/rk3399_ARM-atf/plat/arm/board/corstone700/common/include/
H A Dplatform_def.h55 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
57 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
195 ARM_NS_DRAM1_BASE, \
/rk3399_ARM-atf/plat/arm/common/
H A Darm_pm.c122 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < in arm_validate_ns_entrypoint()
123 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { in arm_validate_ns_entrypoint()
H A Darm_bl1_fwu.c39 .mem_base = ARM_NS_DRAM1_BASE,
/rk3399_ARM-atf/plat/arm/board/fvp_ve/include/
H A Dplatform_def.h34 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
44 #define FVP_VE_SHARED_RAM_BASE ARM_NS_DRAM1_BASE
96 ARM_NS_DRAM1_BASE, \
/rk3399_ARM-atf/include/plat/nuvoton/common/
H A Dnpcm845x_arm_def.h196 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
199 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
255 ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \
523 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE
/rk3399_ARM-atf/plat/arm/board/corstone1000/common/include/
H A Dplatform_def.h106 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
108 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1)
313 ARM_NS_DRAM1_BASE, \
/rk3399_ARM-atf/plat/arm/board/juno/
H A Djuno_ethosn_tzmp1_def.h49 { ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, \
/rk3399_ARM-atf/plat/arm/board/a5ds/include/
H A Dplatform_def.h100 #define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE) macro
120 ARM_NS_DRAM1_BASE, \
/rk3399_ARM-atf/include/plat/arm/common/
H A Darm_def.h237 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
241 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
307 ARM_NS_DRAM1_BASE, \
783 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE
H A Dplat_arm.h64 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
89 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/
H A Dnrd_css_fw_def3.h92 ARM_NS_DRAM1_BASE, \
H A Dnrd_plat_arm_def3.h744 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE macro
748 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
H A Dnrd_pas_def3.h498 ARM_NS_DRAM1_BASE, \
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/
H A Drdv3_common.c150 bank_ptr[0].base = ARM_NS_DRAM1_BASE; in plat_rmmd_load_manifest()