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Searched refs:APU_RPC_BASE (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/
H A Dapusys_power.c137 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, AFC_ENA); in apusys_kernel_apusys_pwr_top_on()
139 mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_SET); in apusys_kernel_apusys_pwr_top_on()
141 ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY, in apusys_kernel_apusys_pwr_top_on()
149 ret = apu_poll(APU_RPC_BASE + APU_RPC_STATUS, in apusys_kernel_apusys_pwr_top_on()
172 mmio_write_32(APU_RPC_BASE + APU_RPC_TOP_CON, REG_WAKEUP_CLR); in apu_sleep_rpc_rcx()
176 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, (RPC_CTRL | RSV10)); in apu_sleep_rpc_rcx()
180 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, CLR_IRQ); in apu_sleep_rpc_rcx()
184 mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_CON, SLEEP_REQ); in apu_sleep_rpc_rcx()
211 ret = apu_poll(APU_RPC_BASE + APU_RPC_INTF_PWR_RDY, in apusys_kernel_apusys_pwr_top_off()
333 mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_SET); in apu_buck_off_cfg()
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H A Dapusys_power.h60 #define APU_RPC_BASE (APU_RPCTOP) macro