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Searched refs:AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_memory_controller.h106 #define AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x7f) >> 0) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_memory_controller.h106 #define AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x7f) >> 0) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c209 rd_latency = AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(data); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c208 rd_latency = AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(data); in configure_ddr_sched_ctrl_regs()