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Searched refs:AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_memory_controller.h50 #define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_memory_controller.h50 #define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c200 AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK, in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c199 AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK, in configure_ddr_sched_ctrl_regs()