Home
last modified time | relevance | path

Searched refs:AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_memory_controller.h58 #define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_memory_controller.h58 #define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c201 AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(ddr_conf)); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c200 AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(ddr_conf)); in configure_ddr_sched_ctrl_regs()