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Searched refs:AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_memory_controller.h55 #define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10 macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_memory_controller.h55 #define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c288 faw_bank << AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST | in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c287 faw_bank << AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST | in configure_ddr_sched_ctrl_regs()