| /optee_os/core/drivers/crypto/caam/hal/common/registers/ |
| H A D | rng_regs.h | 27 #define GET_TRNG_SDCTL_ENT_DLY(val) (((val) & BM_TRNG_SDCTL_ENT_DLY) >> 16) argument
28 #define TRNG_SDCTL_ENT_DLY(val) SHIFT_U32(((val) & 0xFFFF), 16) argument
29 #define TRNG_SDCTL_SAMP_SIZE(val) ((val) & 0xFFFF) argument
46 #define TRNG_RTSCMISC_RTY_CNT(val) SHIFT_U32(((val) & (0xF)), 16) argument
48 #define TRNG_RTSCMISC_LRUN_MAX(val) SHIFT_U32(((val) & (0xFF)), 0) argument
53 #define TRNG_RTPKRRNG_PKR_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
58 #define TRNG_RTPKRMAX_PKR_MAX(val) SHIFT_U32(((val) & (0xFFFFFF)), 0) argument
63 #define TRNG_RTSCML_MONO_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 16) argument
65 #define TRNG_RTSCML_MONO_MAX(val) SHIFT_U32(((val) & (0xFFFF)), 0) argument
70 #define TRNG_RTSCR1L_RUN1_RNG(val) SHIFT_U32(((val) & (0x7FFF)), 16) argument
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| H A D | version_regs.h | 15 #define GET_CTPR_MS_RNG_I(val) (((val) & BM_CTPR_MS_RNG_I) >> 8) argument
19 #define GET_CTPR_LS_SPLIT_KEY(val) (((val) & BM_CTPR_LS_SPLIT_KEY) >> 14) argument
24 #define GET_SMVID_MS_MAX_NPAG(val) (((val) & BM_SMVID_MS_MAX_NPAG) >> 16) argument
26 #define GET_SMVID_MS_NPRT(val) (((val) & BM_SMVID_MS_NPRT) >> 12) argument
30 #define GET_SMVID_LS_PSIZ(val) (((val) & BM_SMVID_LS_PSIZ) >> 16) argument
35 #define GET_CCBVID_CAAM_ERA(val) (((val) & BM_CCBVID_CAAM_ERA) >> 24) argument
40 #define GET_CHAVID_LS_RNGVID(val) (((val) & BM_CHAVID_LS_RNGVID) >> 16) argument
48 #define GET_CHANUM_MS_JRNUM(val) (((val) & BM_CHANUM_MS_JRNUM) >> 28) argument
52 #define GET_CHANUM_LS_PKNUM(val) (((val) & BM_CHANUM_LS_PKNUM) >> 28) argument
54 #define GET_CHANUM_LS_MDNUM(val) (((val) & BM_CHANUM_LS_MDNUM) >> 12) argument
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| H A D | sm_regs.h | 34 #define SM_SMCSR_CERR(val) (((val) >> 14) & 0x3) argument
37 #define SM_SMCSR_AERR(val) (((val) >> 12) & 0x3) argument
39 #define SM_SMCSR_PO(val) (((val) >> 6) & 0x3) argument
44 #define SM_SMCSR_PRTN(val) ((val) & 0x3) argument
49 #define SM_SMPO_OWNER(val, prtn) (((val) >> SM_SMPO_PART(prtn)) & 0x3) argument
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| /optee_os/core/drivers/crypto/caam/hal/common/ |
| H A D | hal_ctrl.c | 22 uint32_t val = io_caam_read32(baseaddr + CCBVID); in caam_hal_ctrl_era() local
24 return GET_CCBVID_CAAM_ERA(val); in caam_hal_ctrl_era()
29 uint32_t val = 0; in caam_hal_ctrl_jrnum() local
33 val = io_caam_read32(baseaddr + CHANUM_MS); in caam_hal_ctrl_jrnum()
34 jrnum = GET_CHANUM_MS_JRNUM(val); in caam_hal_ctrl_jrnum()
36 val = io_caam_read32(baseaddr + JR_VERSION); in caam_hal_ctrl_jrnum()
37 jrnum = GET_JR_VERSION_JRNUM(val); in caam_hal_ctrl_jrnum()
45 uint32_t val = 0; in caam_hal_ctrl_hash_limit() local
49 val = io_caam_read32(baseaddr + CHANUM_LS); in caam_hal_ctrl_hash_limit()
51 if (GET_CHANUM_LS_MDNUM(val)) { in caam_hal_ctrl_hash_limit()
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| H A D | hal_rng.c | 80 uint32_t val = 0; in caam_hal_rng_kick() local
103 val = io_caam_read32(baseaddr + TRNG_SDCTL); in caam_hal_rng_kick()
104 val = GET_TRNG_SDCTL_ENT_DLY(val); in caam_hal_rng_kick()
106 if (ent_delay < val) { in caam_hal_rng_kick()
111 ent_delay = val; in caam_hal_rng_kick()
142 val = io_caam_read32(baseaddr + TRNG_MCTL); in caam_hal_rng_kick()
147 val &= ~BM_TRNG_MCTL_SAMP_MODE; in caam_hal_rng_kick()
148 val |= TRNG_MCTL_SAMP_MODE_RAW_ES_SC; in caam_hal_rng_kick()
150 val &= ~(TRNG_MCTL_PRGM | TRNG_MCTL_ACC); in caam_hal_rng_kick()
151 io_caam_write32(baseaddr + TRNG_MCTL, val); in caam_hal_rng_kick()
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| H A D | hal_jr.c | 158 uint32_t val = 0; in caam_hal_jr_check_ack_itr() local
160 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_check_ack_itr()
162 if ((val & JRX_JRINTR_JRI) == JRX_JRINTR_JRI) { in caam_hal_jr_check_ack_itr()
174 uint32_t val = 0; in caam_hal_jr_halt() local
183 val = io_caam_read32(baseaddr + JRX_IRSR); in caam_hal_jr_halt()
184 if ((caam_hal_jr_read_nbslot_available(baseaddr) == val) && in caam_hal_jr_halt()
191 val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_halt()
192 val &= BM_JRX_JRINTR_HALT; in caam_hal_jr_halt()
193 } while ((val != JRINTR_HALT_DONE) && --timeout); in caam_hal_jr_halt()
204 uint32_t val = 0; in caam_hal_jr_flush() local
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| /optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/ |
| H A D | ctrl_regs.h | 15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
38 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0xF, 0) argument
41 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0xF, 16) argument
43 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0xF, 0) argument
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| /optee_os/core/include/ |
| H A D | io.h | 25 static inline void io_write8(vaddr_t addr, uint8_t val) in io_write8() argument
27 *(volatile uint8_t *)addr = val; in io_write8()
30 static inline void io_write16(vaddr_t addr, uint16_t val) in io_write16() argument
32 *(volatile uint16_t *)addr = val; in io_write16()
35 static inline void io_write32(vaddr_t addr, uint32_t val) in io_write32() argument
37 *(volatile uint32_t *)addr = val; in io_write32()
40 static inline void io_write64(vaddr_t addr, uint64_t val) in io_write64() argument
42 *(volatile uint64_t *)addr = val; in io_write64()
65 static inline void io_mask8(vaddr_t addr, uint8_t val, uint8_t mask) in io_mask8() argument
67 io_write8(addr, (io_read8(addr) & ~mask) | (val & mask)); in io_mask8()
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| /optee_os/core/drivers/crypto/stm32/ |
| H A D | ecc.c | 96 d.val = calloc(1, bytes); in stm32_gen_keypair()
98 if (!d.val) in stm32_gen_keypair()
102 res = crypto_rng_read(d.val, d.size); in stm32_gen_keypair()
104 free(d.val); in stm32_gen_keypair()
108 pk.x.val = calloc(1, bytes); in stm32_gen_keypair()
110 if (!pk.x.val) { in stm32_gen_keypair()
111 free(d.val); in stm32_gen_keypair()
115 pk.y.val = calloc(1, bytes); in stm32_gen_keypair()
117 if (!pk.y.val) { in stm32_gen_keypair()
118 free(pk.x.val); in stm32_gen_keypair()
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| /optee_os/core/drivers/qcom/ramblur/ |
| H A D | ramblur_pimem_v3.c | 39 static inline void out_dword(uint32_t offset, uint32_t val) in out_dword() argument
41 io_write32(ramblur_va + (vaddr_t)offset, val); in out_dword()
50 uint32_t val, uint32_t current_val) in out_dword_masked_ns() argument
54 new_val = (current_val & ~mask) | (val & mask); in out_dword_masked_ns()
58 static inline void readback_sync(uint32_t reg, uint32_t val, uint32_t mask, in readback_sync() argument
65 while (val != (in_dword_masked(reg, mask) >> shift)) in readback_sync()
73 uint32_t val = BIT(RAMBLUR_WINn_CTL_WIN_ENABLE_SHFT); in enable() local
75 out_dword_masked_ns(reg, mask, val, RAMBLUR_WINn_CTL_INI(window)); in enable()
80 val = in_dword_masked(reg, mask) >> in enable()
82 } while (val != 1U); in enable()
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| /optee_os/core/lib/libfdt/ |
| H A D | fdt_addresses.c | 17 uint32_t val; in fdt_cells() local
27 val = fdt32_to_cpu(*c); in fdt_cells()
28 if (val > FDT_MAX_NCELLS) in fdt_cells()
31 return (int)val; in fdt_cells()
36 int val; in fdt_address_cells() local
38 val = fdt_cells(fdt, nodeoffset, "#address-cells"); in fdt_address_cells()
39 if (val == 0) in fdt_address_cells()
41 if (val == -FDT_ERR_NOTFOUND) in fdt_address_cells()
43 return val; in fdt_address_cells()
48 int val; in fdt_size_cells() local
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| /optee_os/core/include/dt-bindings/gpio/ |
| H A D | atmel,piobu.h | 11 #define PIOBU_PIN_AFV(val) (((val) & PIOBU_PIN_AFV_MASK) >> \ argument
16 #define PIOBU_PIN_RFV(val) (((val) & PIOBU_PIN_RFV_MASK) >> \ argument
21 #define PIOBU_PIN_PULL_MODE(val) (((val) & PIOBU_PIN_PULL_MODE_MASK) >> \ argument
29 #define PIOBU_PIN_DEF_LEVEL(val) (((val) & PIOBU_PIN_DEF_LEVEL_MASK) >> \ argument
36 #define PIOBU_PIN_WAKEUP(val) (((val) & PIOBU_PIN_WAKEUP_MASK) >> \ argument
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| /optee_os/core/drivers/crypto/caam/hal/ls/registers/ |
| H A D | ctrl_regs.h | 15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4) argument
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0) argument
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16) argument
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0) argument
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| /optee_os/core/drivers/ |
| H A D | imsic.c | 61 static void imsic_csr_write(unsigned long reg, unsigned long val) in imsic_csr_write() argument
64 write_csr(CSR_XIREG, val); in imsic_csr_write()
73 static void imsic_csr_set(unsigned long reg, unsigned long val) in imsic_csr_set() argument
76 set_csr(CSR_XIREG, val); in imsic_csr_set()
79 static void imsic_csr_clear(unsigned long reg, unsigned long val) in imsic_csr_clear() argument
82 clear_csr(CSR_XIREG, val); in imsic_csr_clear()
107 uint32_t val = swap_csr(CSR_XTOPEI, 0); in imsic_claim_interrupt() local
109 return val >> IMSIC_TOPEI_ID_SHIFT; in imsic_claim_interrupt()
113 bool pend, bool val) in imsic_local_eix_update() argument
132 if (val) in imsic_local_eix_update()
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| H A D | dra7_rng.c | 108 uint32_t val[2]; in hw_get_random_bytes() member
122 dra7_rng_read64(&fifo.val[0], &fifo.val[1]); in hw_get_random_bytes()
135 uint32_t val; in dra7_rng_init() local
153 val = 0; in dra7_rng_init()
156 val |= RNG_CONFIG_MIN_REFIL_CYCLES << in dra7_rng_init()
158 val |= RNG_CONFIG_MAX_REFIL_CYCLES << in dra7_rng_init()
160 io_write32(rng + RNG_CONFIG, val); in dra7_rng_init()
173 val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT; in dra7_rng_init()
179 val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT; in dra7_rng_init()
180 io_write32(rng + RNG_ALARMCNT, val); in dra7_rng_init()
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| H A D | imx_ocotp.c | 83 TEE_Result imx_ocotp_read(unsigned int bank, unsigned int word, uint32_t *val) in imx_ocotp_read() argument
87 if (!val) in imx_ocotp_read()
110 *val = io_read32(g_base_addr + OCOTP_SHADOW_OFFSET(bank, word)); in imx_ocotp_read()
112 DMSG("OCOTP Bank %d Word %d Fuse 0x%" PRIx32, bank, word, *val); in imx_ocotp_read()
122 uint32_t val = 0; in ocotp_get_die_id_mx7ulp() local
125 res = imx_ocotp_read(1, 6, &val); in ocotp_get_die_id_mx7ulp()
128 uid = val & GENMASK_32(15, 0); in ocotp_get_die_id_mx7ulp()
130 res = imx_ocotp_read(1, 5, &val); in ocotp_get_die_id_mx7ulp()
133 uid = SHIFT_U64(uid, 16) | (val & GENMASK_32(15, 0)); in ocotp_get_die_id_mx7ulp()
135 res = imx_ocotp_read(1, 4, &val); in ocotp_get_die_id_mx7ulp()
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| /optee_os/lib/libutils/ext/include/ |
| H A D | atomic.h | 46 static inline void atomic_store_int(int *p, int val) in atomic_store_int() argument
48 __compiler_atomic_store(p, val); in atomic_store_int()
51 static inline void atomic_store_short(short int *p, short int val) in atomic_store_short() argument
53 __compiler_atomic_store(p, val); in atomic_store_short()
56 static inline void atomic_store_uint(unsigned int *p, unsigned int val) in atomic_store_uint() argument
58 __compiler_atomic_store(p, val); in atomic_store_uint()
61 static inline void atomic_store_u32(uint32_t *p, uint32_t val) in atomic_store_u32() argument
63 __compiler_atomic_store(p, val); in atomic_store_u32()
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| /optee_os/core/arch/arm/include/ |
| H A D | arm32.h | 241 uint32_t val; in read_pc() local
243 asm volatile ("adr %0, ." : "=r" (val)); in read_pc()
244 return val; in read_pc()
249 uint32_t val; in read_sp() local
251 asm volatile ("mov %0, sp" : "=r" (val)); in read_sp()
252 return val; in read_sp()
257 uint32_t val; in read_lr() local
259 asm volatile ("mov %0, lr" : "=r" (val)); in read_lr()
260 return val; in read_lr()
265 uint32_t val; in read_fp() local
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| H A D | arm32_macros.S | 11 .macro mov_imm reg, val argument
12 .if ((\val) & 0xffff0000) == 0
13 movw \reg, #(\val)
15 movw \reg, #((\val) & 0xffff)
16 movt \reg, #((\val) >> 16)
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| /optee_os/core/drivers/crypto/caam/hal/imx_8ulp/ |
| H A D | hal_jr.c | 28 uint32_t val = 0; in caam_hal_jr_setowner() local
34 val = io_caam_read32(ctrl_base + JRxDID_MS(jr_idx)); in caam_hal_jr_setowner()
35 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
53 if (val & JRxDID_MS_LDID) { in caam_hal_jr_setowner()
60 jr_idx, val, cfg_ms); in caam_hal_jr_setowner()
61 if ((cfg_ms | JRxDID_MS_LDID) == val) { in caam_hal_jr_setowner()
63 val = io_caam_read32(ctrl_base + JRxDID_LS(jr_idx)); in caam_hal_jr_setowner()
66 jr_idx, val, cfg_ls); in caam_hal_jr_setowner()
67 if (val == cfg_ls) in caam_hal_jr_setowner()
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| /optee_os/core/drivers/crypto/caam/hal/imx_8m/ |
| H A D | hal_jr.c | 27 uint32_t val = 0; in caam_hal_jr_setowner() local
33 val = io_caam_read32(ctrl_base + JRxDID_MS(jr_idx)); in caam_hal_jr_setowner()
34 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
52 if (val & JRxDID_MS_LDID) { in caam_hal_jr_setowner()
59 jr_idx, val, cfg_ms); in caam_hal_jr_setowner()
60 if ((cfg_ms | JRxDID_MS_LDID) == val) { in caam_hal_jr_setowner()
62 val = io_caam_read32(ctrl_base + JRxDID_LS(jr_idx)); in caam_hal_jr_setowner()
65 jr_idx, val, cfg_ls); in caam_hal_jr_setowner()
66 if (val == cfg_ls) in caam_hal_jr_setowner()
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| /optee_os/core/arch/arm/plat-imx/ |
| H A D | imx_pl310.c | 30 uint32_t val = 0; in arm_cl2_config() local
51 val = PL310_PREFETCH_CTRL_INIT; in arm_cl2_config()
57 val &= ~PL310_PREFETCH_DOUBLE_LINEFILL; in arm_cl2_config()
59 io_write32(pl310_base + PL310_PREFETCH_CTRL, val); in arm_cl2_config()
69 uint32_t val __maybe_unused; in arm_cl2_enable()
76 val = io_read32(pl310_base + PL310_AUX_CTRL); in arm_cl2_enable()
77 if (val & PL310_AUX_CTRL_FLZW) in arm_cl2_enable()
119 uint32_t val = PL310_DEBUG_CTRL_DISABLE_WRITEBACK | in pl310_disable_writeback() local
122 io_write32(base + PL310_DEBUG_CTRL, val); in pl310_disable_writeback()
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| /optee_os/core/drivers/crypto/caam/hal/imx_6_7/ |
| H A D | hal_jr.c | 27 uint32_t val = 0; in caam_hal_jr_setowner() local
33 val = io_caam_read32(ctrl_base + JRxMIDR_MS(jr_idx)); in caam_hal_jr_setowner()
34 HAL_TRACE("JR%" PRIu32 "MIDR_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
53 if (val & JRxMIDR_MS_LMID) { in caam_hal_jr_setowner()
60 jr_idx, val, cfg_ms); in caam_hal_jr_setowner()
61 if ((cfg_ms | JRxMIDR_MS_LMID) == val) { in caam_hal_jr_setowner()
66 val = io_caam_read32(ctrl_base + JRxMIDR_LS(jr_idx)); in caam_hal_jr_setowner()
69 jr_idx, val, cfg_ls); in caam_hal_jr_setowner()
70 if (val == cfg_ls) in caam_hal_jr_setowner()
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| /optee_os/core/lib/libfdt/include/ |
| H A D | libfdt.h | 248 static inline void fdt_set_##name(void *fdt, uint32_t val) \
251 fdth->name = cpu_to_fdt32(val); \
1219 uint32_t idx, const void *val,
1253 const void *val, int len);
1285 const char *name, uint32_t val) in fdt_setprop_inplace_u32() argument
1287 fdt32_t tmp = cpu_to_fdt32(val); in fdt_setprop_inplace_u32()
1320 const char *name, uint64_t val) in fdt_setprop_inplace_u64() argument
1322 fdt64_t tmp = cpu_to_fdt64(val); in fdt_setprop_inplace_u64()
1332 const char *name, uint32_t val) in fdt_setprop_inplace_cell() argument
1334 return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); in fdt_setprop_inplace_cell()
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| /optee_os/lib/libmbedtls/mbedtls/library/ |
| H A D | asn1write.c | 202 static int asn1_write_tagged_int(unsigned char **p, const unsigned char *start, int val, int tag) in asn1_write_tagged_int() argument
211 *--(*p) = val & 0xff; in asn1_write_tagged_int()
212 val >>= 8; in asn1_write_tagged_int()
213 } while (val > 0); in asn1_write_tagged_int()
226 int mbedtls_asn1_write_int(unsigned char **p, const unsigned char *start, int val) in mbedtls_asn1_write_int() argument
228 return asn1_write_tagged_int(p, start, val, MBEDTLS_ASN1_INTEGER); in mbedtls_asn1_write_int()
231 int mbedtls_asn1_write_enum(unsigned char **p, const unsigned char *start, int val) in mbedtls_asn1_write_enum() argument
233 return asn1_write_tagged_int(p, start, val, MBEDTLS_ASN1_ENUMERATED); in mbedtls_asn1_write_enum()
379 const unsigned char *val, in mbedtls_asn1_store_named_data() argument
402 cur->val.len = val_len; in mbedtls_asn1_store_named_data()
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