| /optee_os/core/arch/arm/sm/ |
| H A D | pm_a32.S | 28 mov r5, sp 32 mov r1, r5 51 ubfx r5, r4, #4, #12 53 cmp r5, r4 56 cmp r5, r4 59 cmp r5, r4 66 read_diag r5 67 stmia r0!, {r4 - r5} 70 read_tpidruro r5 71 stmia r0!, {r4 - r5} [all …]
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| /optee_os/ldelf/ |
| H A D | start_a32.S | 25 ldr r5, reloc_begin_rel 27 add r5, r5, r4 29 cmp r5, r6 35 1: ldmia r5!, {r7-r8} /* r7 == r_offset, r8 = r_info */ 47 cmp r5, r6
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| H A D | syscalls_a32.S | 21 push {r5-r7, lr} 22 UNWIND( .save {r5-r7, lr}) 32 add r5, sp, #(4 * 4) 36 pop {r5-r7, pc}
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| /optee_os/core/arch/arm/kernel/ |
| H A D | arch_scall_a32.S | 20 push {r5-r9, lr} 24 ldr r5, [r8, #THREAD_SCALL_REG_R5] 41 mov r1, r5 57 pop {r5-r9, pc}
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| H A D | entry_a32.S | 44 mov r5, r1 57 mov r1, r5 204 mov r5, r1 531 mov r1, r5 819 mov r2, r5 /* std bootarg #1 for register R1 */ 857 push {r4-r5} 898 ldr r5, [r4, r1] 899 add r5, r5, r0 900 str r5, [r4, r1] 905 pop {r4-r5} [all …]
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| H A D | thread_optee_smc_a32.S | 174 push {r4, r5} /* Pass these following the arm32 calling convention */ 208 ldr r5, [sp] /* Get pointer to rv[] */ 218 ldm r5, {r1-r3} /* Load rv[] into r0-r2 */
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| H A D | thread_a32.S | 190 mov r5, r12 /* Save CPSR in a preserved register */ 217 mov r0, r5 /* Return original CPSR */ 331 push {r1, r2, r4, r5} 353 str r2, [r5] 928 read_vbar r5 /* This register must be preserved */ 929 sub r3, r5, r2 1002 write_vbar r5
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| H A D | cache_helpers_a32.S | 126 clz r5, r4 // r5 = the bit position of the way size increment 133 orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
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| H A D | arch_scall.c | 32 .r5 = pushed[6], in save_panic_regs_a32_ta()
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| H A D | stmm_sp.c | 49 #define SVC_REGS_A5(_regs) ((_regs)->r5) 539 spc->regs.r5 = 0; in stmm_enter_invoke_cmd() 621 spc->regs.r5 = regs->r5; in save_sp_ctx()
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| H A D | asm-defines.c | 29 DEFINE(THREAD_SCALL_REG_R5, offsetof(struct thread_scall_regs, r5));
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| H A D | abort.c | 57 state.registers[5] = ai->regs->r5; in __print_stack_unwind() 173 EMSG_RAW(" r1 0x%08x r5 0x%08x r9 0x%08x sp 0x%08x", in __print_abort_info() 174 ai->regs->r1, ai->regs->r5, ai->regs->r9, sp); in __print_abort_info()
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| H A D | thread.c | 179 thread->regs.r5 = a5; in init_regs()
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| /optee_os/lib/libutee/arch/arm/ |
| H A D | utee_syscalls_a32.S | 18 push {r5-r7,lr} 19 UNWIND( .save {r5-r7,lr}) 42 add r5, sp, #(4 * 4) 45 pop {r5-r7,pc}
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| /optee_os/lib/libutils/isoc/arch/arm/ |
| H A D | setjmp_a32.S | 100 stmia r0!, {r4, r5, r6, r7} 105 mov r5, sp 107 stmia r0!, {r1, r2, r3, r4, r5, r6} 110 ldmia r0!, {r4, r5, r6, r7} 121 ldmia r0!, {r2, r3, r4, r5, r6} 125 mov fp, r5 130 ldmia r0!, {r4, r5, r6, r7}
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| /optee_os/core/arch/arm/crypto/ |
| H A D | aes_modes_armv8a_ce_a32.S | 221 ldrd r4, r5, [sp, #16] 222 vld1.8 {q0}, [r5] 231 vst1.8 {q0}, [r5] 242 ldrd r4, r5, [sp, #16] 243 vld1.8 {q6}, [r5] @ keep iv in q6 274 vst1.8 {q6}, [r5] @ keep iv in q6 285 ldrd r4, r5, [sp, #16] 286 vld1.8 {q6}, [r5] @ load ctr 335 vst1.8 {q6}, [r5] 378 ldr r5, [sp, #24] [all …]
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| /optee_os/core/arch/arm/include/sm/ |
| H A D | sm.h | 60 uint32_t r5; member 77 uint32_t r5; member
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| /optee_os/core/arch/arm/include/kernel/ |
| H A D | thread_arch.h | 180 uint32_t r5; member 241 uint32_t r5; member 300 uint32_t r5; member
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| /optee_os/core/arch/arm/plat-ti/ |
| H A D | a9_plat_init.S | 80 mov r0, r5
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| /optee_os/core/kernel/ |
| H A D | ldelf_loader.c | 247 arg->arm32.regs[5] = tsd->abort_regs.r5; in ldelf_dump_state()
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| /optee_os/core/drivers/pm/sam/ |
| H A D | pm_suspend.S | 27 tmp2 .req r5
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