Searched refs:core_idx (Results 1 – 6 of 6) sorted by relevance
| /optee_os/core/arch/arm/plat-sunxi/ |
| H A D | psci.c | 69 int psci_cpu_on(uint32_t core_idx, uint32_t entry, in psci_cpu_on() argument
83 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE)) in psci_cpu_on()
87 boot_set_core_ns_entry(core_idx, entry, context_id); in psci_cpu_on()
92 DMSG("set entry address for CPU %d", core_idx); in psci_cpu_on()
96 DMSG("assert reset on target CPU %d", core_idx); in psci_cpu_on()
97 io_write32(cpucfg + REG_CPUCFG_CPU_RST(core_idx), 0); in psci_cpu_on()
100 DMSG("invalidate L1 cache for CPU %d", core_idx); in psci_cpu_on()
101 io_clrbits32(cpucfg + REG_CPUCFG_GEN_CTRL, BIT32(core_idx)); in psci_cpu_on()
104 DMSG("lock CPU %d", core_idx); in psci_cpu_on()
105 io_clrbits32(cpucfg + REG_CPUCFG_DBG_CTRL1, BIT32(core_idx)); in psci_cpu_on()
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| /optee_os/core/drivers/pm/imx/ |
| H A D | psci.c | 52 int psci_cpu_on(uint32_t core_idx, uint32_t entry, uint32_t context_id) in psci_cpu_on() argument
54 if (core_idx == 0 || core_idx >= CFG_TEE_CORE_NB_CORE) in psci_cpu_on()
58 boot_set_core_ns_entry(core_idx, entry, context_id); in psci_cpu_on()
59 imx_set_src_gpr_entry(core_idx, virt_to_phys((void *)TEE_LOAD_ADDR)); in psci_cpu_on()
63 imx_src_release_secondary_core(core_idx); in psci_cpu_on()
65 imx_src_release_secondary_core(core_idx); in psci_cpu_on()
66 imx_set_src_gpr_arg(core_idx, 0); in psci_cpu_on()
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| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | psci_rk322x.c | 248 int psci_cpu_on(uint32_t core_idx, uint32_t entry, in psci_cpu_on() argument
255 core_idx &= MPIDR_CPU_MASK; in psci_cpu_on()
256 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE)) in psci_cpu_on()
259 DMSG("core_id: %" PRIu32, core_idx); in psci_cpu_on()
262 boot_set_core_ns_entry(core_idx, entry, context_id); in psci_cpu_on()
265 if (!core_held_in_reset(core_idx)) { in psci_cpu_on()
266 wfei = wait_core_wfe_i(core_idx); in psci_cpu_on()
269 core_idx); in psci_cpu_on()
275 io_write32(cru_base + CRU_SOFTRST_CON(0), CORE_SOFT_RESET(core_idx)); in psci_cpu_on()
281 io_write32(cru_base + CRU_SOFTRST_CON(0), CORE_SOFT_RELEASE(core_idx)); in psci_cpu_on()
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| /optee_os/core/arch/arm/plat-hisilicon/ |
| H A D | psci.c | 62 int psci_cpu_on(uint32_t core_idx, uint32_t entry, in psci_cpu_on() argument
66 size_t pos = get_core_pos_mpidr(core_idx); in psci_cpu_on()
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| /optee_os/core/include/kernel/ |
| H A D | boot.h | 93 void boot_set_core_ns_entry(size_t core_idx, uintptr_t entry,
96 int boot_core_release(size_t core_idx, paddr_t entry);
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| /optee_os/core/arch/arm/kernel/ |
| H A D | boot.c | 1197 void boot_set_core_ns_entry(size_t core_idx, uintptr_t entry, in boot_set_core_ns_entry() argument
1200 ns_entry_contexts[core_idx].entry_point = entry; in boot_set_core_ns_entry()
1201 ns_entry_contexts[core_idx].context_id = context_id; in boot_set_core_ns_entry()
1205 int boot_core_release(size_t core_idx, paddr_t entry) in boot_core_release() argument
1207 if (!core_idx || core_idx >= CFG_TEE_CORE_NB_CORE) in boot_core_release()
1210 ns_entry_contexts[core_idx].entry_point = entry; in boot_core_release()
1212 spin_table[core_idx] = 1; in boot_core_release()
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