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Searched refs:c0 (Results 1 – 6 of 6) sorted by relevance

/optee_os/core/arch/arm/kernel/
H A Darm32_sysreg.txt12 AIDR c0 1 c0 7 RO IMPLEMENTATION DEFINED Auxiliary ID Register
13 CCSIDR c0 1 c0 0 RO Cache Size ID Registers
14 CLIDR c0 1 c0 1 RO Cache Level ID Register
15 CSSELR c0 2 c0 0 RW Cache Size Selection Register
16 CTR c0 0 c0 1 RO Cache Type Register
17 ID_AFR0 c0 0 c1 3 RO Auxiliary Feature Register 0
18 ID_DFR0 c0 0 c1 2 RO Debug Feature Register 0
19 ID_ISAR0 c0 0 c2 0 RO Instruction Set Attribute Register 0
20 ID_ISAR1 c0 0 c2 1 RO Instruction Set Attribute Register 1
21 ID_ISAR2 c0 0 c2 2 RO Instruction Set Attribute Register 2
[all …]
/optee_os/core/arch/arm/include/
H A Darm32_macros_cortex_a9.S32 mcr p15, 0, \reg, c15, c0, 0
36 mrc p15, 0, \reg, c15, c0, 0
40 mcr p15, 0, \reg, c15, c0, 1
44 mrc p15, 0, \reg, c15, c0, 1
/optee_os/core/arch/arm/plat-hisilicon/
H A Dhi3519av100_plat_init.S56 mrc p15, 4, r2, c1, c0, 1
58 mcr p15, 4, r2, c1, c0, 1
65 mrc p15, 0, r2, c1, c0, 1
67 mcr p15, 0, r2, c1, c0, 1
/optee_os/lib/libutils/ext/include/
H A Dfault_mitigation.h205 #define __ftmn_step_count_1(c0) ((c0) * FTMN_INCR0) argument
206 #define __ftmn_step_count_2(c0, c1) \ argument
207 (__ftmn_step_count_1(c0) + (c1) * FTMN_INCR1)
208 #define __ftmn_step_count_3(c0, c1, c2) \ argument
209 (__ftmn_step_count_2(c0, c1) + (c2) * FTMN_INCR2)
210 #define __ftmn_step_count_4(c0, c1, c2, c3) \ argument
211 (__ftmn_step_count_3(c0, c1, c2) + (c3) * FTMN_INCR3)
212 #define __ftmn_step_count_5(c0, c1, c2, c3, c4) \ argument
213 (__ftmn_step_count_4(c0, c1, c2, c3) + (c4) * FTMN_INCR4)
214 #define __ftmn_step_count_6(c0, c1, c2, c3, c4, c5) \ argument
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/optee_os/lib/libutee/arch/arm/
H A Darm32_user_sysreg.txt12 CNTFRQ c14 0 c0 0 RW Counter Frequency register
/optee_os/core/arch/arm/crypto/
H A Dsm4_armv8a_aese_a64.S159 .macro round, c0, c1, c2, c3, k
175 eor \c0, \c0, tmpw2