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Searched refs:addr (Results 1 – 25 of 96) sorted by relevance

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/optee_os/lib/libutils/ext/include/
H A Dmemtag.h30 void *(*set_tags)(void *addr, size_t size, uint8_t tag);
31 void *(*set_random_tags)(void *addr, size_t size);
32 void (*clear_mem)(void *addr, size_t size);
33 uint8_t (*read_tag)(const void *addr);
39 static inline void *__memtag_disabled_set_tags(void *addr, size_t size __unused, in __memtag_disabled_set_tags() argument
42 return addr; in __memtag_disabled_set_tags()
45 static inline void *__memtag_disabled_set_random_tags(void *addr, in __memtag_disabled_set_random_tags() argument
48 return addr; in __memtag_disabled_set_random_tags()
51 static inline void __memtag_disabled_clear_mem(void *addr, size_t size) in __memtag_disabled_clear_mem() argument
53 memset(addr, 0, size); in __memtag_disabled_clear_mem()
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/optee_os/core/arch/arm/plat-sam/
H A Dplatform_sama7g5.c42 .addr = DWDT_BASE_ADDRESS,
47 .addr = DWDT_BASE_ADDRESS,
52 .addr = DWDT_BASE_ADDRESS,
57 .addr = SCKC_BASE_ADDRESS,
62 .addr = SHDWC_BASE_ADDRESS,
67 .addr = RSTC_BASE_ADDRESS,
72 .addr = RTC_BASE_ADDRESS,
77 .addr = RTT_BASE_ADDRESS,
82 .addr = CHIPID_BASE_ADDRESS,
87 .addr = PMC_BASE_ADDRESS,
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H A Dplatform_sama5d2.c67 .addr = AT91C_BASE_PMC,
78 .addr = AT91C_BASE_PITC,
84 .addr = AT91C_BASE_WDT,
90 .addr = AT91C_BASE_GMAC,
96 .addr = AT91C_BASE_XDMAC0,
102 .addr = AT91C_BASE_XDMAC1,
108 .addr = AT91C_BASE_ICM,
114 .addr = AT91C_BASE_AES,
120 .addr = AT91C_BASE_AESB,
126 .addr = AT91C_BASE_TDES,
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/optee_os/core/include/
H A Dio.h25 static inline void io_write8(vaddr_t addr, uint8_t val) in io_write8() argument
27 *(volatile uint8_t *)addr = val; in io_write8()
30 static inline void io_write16(vaddr_t addr, uint16_t val) in io_write16() argument
32 *(volatile uint16_t *)addr = val; in io_write16()
35 static inline void io_write32(vaddr_t addr, uint32_t val) in io_write32() argument
37 *(volatile uint32_t *)addr = val; in io_write32()
40 static inline void io_write64(vaddr_t addr, uint64_t val) in io_write64() argument
42 *(volatile uint64_t *)addr = val; in io_write64()
45 static inline uint8_t io_read8(vaddr_t addr) in io_read8() argument
47 return *(volatile uint8_t *)addr; in io_read8()
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/optee_os/core/kernel/
H A Dasan.c49 static bool addr_crosses_scale_boundary(vaddr_t addr, size_t size) in addr_crosses_scale_boundary() argument
51 return (addr >> ASAN_BLOCK_SHIFT) != in addr_crosses_scale_boundary()
52 ((addr + size - 1) >> ASAN_BLOCK_SHIFT); in addr_crosses_scale_boundary()
189 static void asan_report(vaddr_t addr, size_t size) in asan_report() argument
196 b = ROUNDDOWN(addr, ASAN_BLOCK_SIZE) - ASAN_BLOCK_SIZE; in asan_report()
197 e = ROUNDDOWN(addr, ASAN_BLOCK_SIZE) + ASAN_BLOCK_SIZE; in asan_report()
216 addr, size); in asan_report()
221 static __always_inline bool asan_shadow_1byte_isvalid(vaddr_t addr) in asan_shadow_1byte_isvalid() argument
223 int8_t last = (addr & ASAN_BLOCK_MASK) + 1; in asan_shadow_1byte_isvalid()
224 int8_t *byte = va_to_shadow((void *)addr); in asan_shadow_1byte_isvalid()
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/optee_os/core/drivers/
H A Dlpc_uart.c21 static void lpc_byte_read(paddr_t addr, uint8_t *data) in lpc_byte_read() argument
26 io_write32(LPC_CMD_REG_OFFSET + addr, LPC_SINGLE_READ); in lpc_byte_read()
28 io_write32(LPC_OP_LEN_REG_OFFSET + addr, 1); in lpc_byte_read()
29 io_write32(LPC_ADDR_REG_OFFSET + addr, UART_BASE + UART_LSR); in lpc_byte_read()
31 io_write32(LPC_START_REG_OFFSET + addr, 1); in lpc_byte_read()
33 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_read()
38 status = io_read32(LPC_IRQ_ST_REG_OFFSET + addr); in lpc_byte_read()
41 io_write32(LPC_IRQ_ST_REG_OFFSET + addr, LPC_IRQ_ST_ON); in lpc_byte_read()
43 if (io_read32(LPC_OP_STATUS_REG_OFFSET + addr) & LPC_IRQ_ST_ON) in lpc_byte_read()
44 *data = io_read32(LPC_RDATA_REG_OFFSET + addr); in lpc_byte_read()
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H A Dversal_trng.c175 vaddr_t addr; member
487 static uint32_t trng_read32(vaddr_t addr, size_t off) in trng_read32() argument
489 return io_read32(addr + off); in trng_read32()
492 static void trng_write32(vaddr_t addr, size_t off, uint32_t val) in trng_write32() argument
494 io_write32(addr + off, val); in trng_write32()
497 static void trng_clrset32(vaddr_t addr, size_t off, uint32_t mask, uint32_t val) in trng_clrset32() argument
499 io_clrsetbits32(addr + off, mask, mask & val); in trng_clrset32()
513 trng_write32(trng->cfg.addr, off, 0); in trng_write32_range()
522 trng_write32(trng->cfg.addr, off, val); in trng_write32_range()
526 static TEE_Result trng_wait_for_event(vaddr_t addr, size_t off, uint32_t mask, in trng_wait_for_event() argument
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/optee_os/lib/libutils/ext/arch/arm/
H A Dmemtag.c46 static void *insert_random_tag(void *addr) in insert_random_tag() argument
48 asm volatile("irg %0, %0" : "+r"(addr) : : ); in insert_random_tag()
49 return addr; in insert_random_tag()
52 static void *load_tag(void *addr) in load_tag() argument
54 asm volatile("ldg %0, [%0]" : "+r"(addr) : : ); in load_tag()
55 return addr; in load_tag()
76 static void *set_tags_helper(void *addr, size_t size) in set_tags_helper() argument
78 vaddr_t va = (vaddr_t)addr; in set_tags_helper()
87 return addr; in set_tags_helper()
90 static void *set_tags_dc_helper(void *addr, size_t size) in set_tags_dc_helper() argument
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/optee_os/core/arch/arm/kernel/
H A Dunwind_arm64.c54 vaddr_t *addr = NULL; in unw_get_kernel_stack() local
63 tmp = unw_grow(addr, &size, (n + 1) * sizeof(vaddr_t)); in unw_get_kernel_stack()
66 addr = tmp; in unw_get_kernel_stack()
67 addr[n] = state.pc; in unw_get_kernel_stack()
71 if (addr) { in unw_get_kernel_stack()
72 tmp = unw_grow(addr, &size, (n + 1) * sizeof(vaddr_t)); in unw_get_kernel_stack()
75 addr = tmp; in unw_get_kernel_stack()
76 addr[n] = 0; in unw_get_kernel_stack()
79 return addr; in unw_get_kernel_stack()
82 free(addr); in unw_get_kernel_stack()
H A Dunwind_arm32.c48 bool find_exidx(vaddr_t addr __unused, vaddr_t *idx_start, vaddr_t *idx_end) in find_exidx()
61 vaddr_t *addr = NULL; in unw_get_kernel_stack() local
85 tmp = unw_grow(addr, &size, (n + 1) * sizeof(vaddr_t)); in unw_get_kernel_stack()
88 addr = tmp; in unw_get_kernel_stack()
89 addr[n] = state.registers[PC]; in unw_get_kernel_stack()
93 if (addr) { in unw_get_kernel_stack()
94 tmp = unw_grow(addr, &size, (n + 1) * sizeof(vaddr_t)); in unw_get_kernel_stack()
97 addr = tmp; in unw_get_kernel_stack()
98 addr[n] = 0; in unw_get_kernel_stack()
101 return addr; in unw_get_kernel_stack()
/optee_os/core/arch/arm/plat-ls/
H A Dmain.c78 vaddr_t addr; in plat_primary_init_early() local
95 for (addr = CSU_BASE + CSU_CSL_START; in plat_primary_init_early()
96 addr != CSU_BASE + CSU_CSL_END; in plat_primary_init_early()
97 addr += 4) in plat_primary_init_early()
98 io_write32(addr, __compiler_bswap32(CSU_ACCESS_ALL)); in plat_primary_init_early()
107 for (addr = CSU_BASE + CSU_CSL_START; in plat_primary_init_early()
108 addr != CSU_BASE + CSU_CSL_END; in plat_primary_init_early()
109 addr += 4) in plat_primary_init_early()
110 io_setbits32(addr, in plat_primary_init_early()
170 vaddr_t addr = 0; in get_gic_offset() local
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/optee_os/core/drivers/firewall/
H A Dstm32_rif.c95 bool stm32_rif_semaphore_is_available(vaddr_t addr) in stm32_rif_semaphore_is_available() argument
97 return !(io_read32(addr) & _SEMCR_MUTEX); in stm32_rif_semaphore_is_available()
100 TEE_Result stm32_rif_acquire_semaphore(vaddr_t addr, unsigned int nb_cid_supp) in stm32_rif_acquire_semaphore() argument
105 io_setbits32(addr, _SEMCR_MUTEX); in stm32_rif_acquire_semaphore()
108 if (stm32_rif_semaphore_is_available(addr) || in stm32_rif_acquire_semaphore()
109 ((io_read32(addr) & scid_mask) >> _CIDCFGR_SCID_SHIFT) != RIF_CID1) in stm32_rif_acquire_semaphore()
115 TEE_Result stm32_rif_release_semaphore(vaddr_t addr, unsigned int nb_cid_supp) in stm32_rif_release_semaphore() argument
119 if (stm32_rif_semaphore_is_available(addr)) in stm32_rif_release_semaphore()
123 io_clrbits32(addr, _SEMCR_MUTEX); in stm32_rif_release_semaphore()
126 if (!stm32_rif_semaphore_is_available(addr) && in stm32_rif_release_semaphore()
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/optee_os/scripts/
H A Dmem_usage.py46 def print_sect(name, addr, size, round_up=False, print_num_pages=False): argument
59 printf('%-16s %.8X - %.8X size %.8X %3d KiB', name, addr, addr + size,
117 (_, name, _, addr, offs, size, _,
122 sects.append({'name': name, 'addr': addr,
127 addr = sect['addr']
129 first_addr = addr
130 if int(addr, 16) >= end_of_ram:
132 last_addr = addr
142 addr = int(sect['addr'], 16)
145 if addr >= end_of_ram:
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H A Dsymbolize.py204 def elf_load_addr(self, addr): argument
209 i_addr = int(addr, 16)
224 def elf_for_addr(self, addr): argument
225 l_addr = self.elf_load_addr(addr)
234 def subtract_load_addr(self, addr): argument
235 l_addr = self.elf_load_addr(addr)
238 if int(l_addr, 16) > int(addr, 16):
240 return '0x{:x}'.format(int(addr, 16) - int(l_addr, 16))
242 def resolve(self, addr): argument
243 reladdr = self.subtract_load_addr(addr)
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/optee_os/core/drivers/bnxt/
H A Dbnxt.c48 static void bnxt_prepare_access_window(uint32_t addr) in bnxt_prepare_access_window() argument
50 addr &= BNXT_INDIRECT_BASE_MASK; in bnxt_prepare_access_window()
51 io_write32(bnxt_access_window_virt_addr, addr); in bnxt_prepare_access_window()
54 static vaddr_t bnxt_indirect_tgt_addr(uint32_t addr) in bnxt_indirect_tgt_addr() argument
56 addr &= BNXT_INDIRECT_ADDR_MASK; in bnxt_indirect_tgt_addr()
57 return (vaddr_t)(bnxt_indirect_dest_addr + addr); in bnxt_indirect_tgt_addr()
91 static uint32_t bnxt_read(uint32_t addr) in bnxt_read() argument
93 bnxt_prepare_access_window(addr); in bnxt_read()
94 return io_read32(bnxt_indirect_tgt_addr(addr)); in bnxt_read()
102 static void bnxt_write(uint32_t addr, uint32_t value) in bnxt_write() argument
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/optee_os/core/include/kernel/
H A Dcache_helpers.h20 void dcache_cleaninv_range(void *addr, size_t size);
21 void dcache_clean_range(void *addr, size_t size);
22 void dcache_inv_range(void *addr, size_t size);
23 void dcache_clean_range_pou(void *addr, size_t size);
26 void icache_inv_range(void *addr, size_t size);
27 void icache_inv_user_range(void *addr, size_t size);
/optee_os/core/include/mm/
H A Dcore_mmu.h179 paddr_t addr; member
194 { .name = (_name), .type = (_type), .addr = (_addr), \
207 #define register_phys_mem(type, addr, size) \ argument
208 __register_memory(#addr, (type), (addr), (size), \
211 #define register_phys_mem_ul(type, addr, size) \ argument
212 __register_memory_ul(#addr, (type), (addr), (size), \
216 #define register_phys_mem_pgdir(type, addr, size) \ argument
217 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \
218 ROUNDUP(size + addr - \
219 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \
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/optee_os/core/include/drivers/
H A Dns16550.h48 static inline unsigned int serial_in(vaddr_t addr, uint8_t io_width) in serial_in() argument
51 return io_read32(addr); in serial_in()
53 return io_read8(addr); in serial_in()
56 static inline void serial_out(vaddr_t addr, uint8_t io_width, int ch) in serial_out() argument
59 io_write32(addr, ch); in serial_out()
61 io_write8(addr, ch); in serial_out()
H A Dstm32_rif.h138 bool stm32_rif_semaphore_is_available(vaddr_t addr);
147 TEE_Result stm32_rif_acquire_semaphore(vaddr_t addr,
157 TEE_Result stm32_rif_release_semaphore(vaddr_t addr,
204 static inline bool stm32_rif_semaphore_is_available(vaddr_t addr __unused) in stm32_rif_semaphore_is_available()
210 stm32_rif_acquire_semaphore(vaddr_t addr __unused, in stm32_rif_acquire_semaphore()
217 stm32_rif_release_semaphore(vaddr_t addr __unused, in stm32_rif_release_semaphore()
/optee_os/core/arch/arm/plat-imx/
H A Dtzc380.c32 static int imx_tzc_auto_configure(vaddr_t addr, vaddr_t rsize, uint32_t attr, in imx_tzc_auto_configure() argument
43 addr_imx = addr - CFG_DRAM_BASE; in imx_tzc_auto_configure()
45 addr_imx = addr; in imx_tzc_auto_configure()
52 vaddr_t addr[2] = {0}; in imx_configure_tzasc() local
56 addr[0] = core_mmu_get_va(TZASC_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
61 addr[1] = core_mmu_get_va(TZASC2_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
68 tzc_init(addr[i]); in imx_configure_tzasc()
H A Dimx-common.c27 vaddr_t addr = 0; in imx_get_digprog() local
32 addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC, 0x1000); in imx_get_digprog()
33 if (!addr) in imx_get_digprog()
36 imx_digprog = io_read32(addr + DIGPROG_OFFSET); in imx_get_digprog()
43 addr = core_mmu_get_va(OCOTP_BASE, MEM_AREA_IO_SEC, OCOTP_SIZE); in imx_get_digprog()
44 if (!addr) in imx_get_digprog()
47 if (io_read32(addr + OCOTP_SW_INFO_B1) == OCOTP_SW_MAGIC_B1) in imx_get_digprog()
/optee_os/core/arch/arm/plat-zynq7k/
H A Dmain.c161 static uint32_t write_slcr(uint32_t addr, uint32_t val) in write_slcr() argument
166 if (addr >= slcr_access_range[i] && in write_slcr()
167 addr <= slcr_access_range[i+1]) { in write_slcr()
173 addr + in write_slcr()
175 io_write32(va + addr, val); in write_slcr()
182 static uint32_t read_slcr(uint32_t addr, uint32_t *val) in read_slcr() argument
187 if (addr >= slcr_access_range[i] && in read_slcr()
188 addr <= slcr_access_range[i+1]) { in read_slcr()
194 addr + in read_slcr()
196 *val = io_read32(va + addr); in read_slcr()
/optee_os/core/drivers/i2c/
H A Di2c.c19 paddr_t addr = fdt_reg_base_address(fdt, node); in i2c_create_dev() local
21 if (addr == DT_INFO_INVALID_REG) in i2c_create_dev()
28 i2c_dev->addr = addr; in i2c_create_dev()
/optee_os/core/arch/arm/plat-marvell/armada7k8k/
H A Dhal_sec_perf.c35 #define PHY_2_VIR(addr) ((vaddr_t)phys_to_virt((addr), MEM_AREA_IO_SEC, 1)) argument
152 static int32_t set_range(uint32_t addr, uint32_t size, uint32_t perm) in set_range() argument
159 if (!IS_ALIGNED(addr, SIZE_1M)) { in set_range()
161 addr); in set_range()
171 if (!IS_ALIGNED(addr, size)) { in set_range()
174 size, addr); in set_range()
195 TZ_SET_START_ADDR_L(data, addr); in set_range()
238 static uint32_t _find_granule(uint32_t addr, uint32_t size) in _find_granule() argument
246 if (max_granule <= size && IS_ALIGNED(addr, max_granule)) in _find_granule()
255 static void _set_range(uint32_t addr, uint32_t size, uint32_t perm) in _set_range() argument
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/optee_os/core/mm/
H A Dphys_mem.c68 static bool is_in_pool_range(tee_mm_pool_t *pool, paddr_t addr) in is_in_pool_range() argument
70 return pool && core_is_buffer_inside(addr, 1, pool->lo, pool->size); in is_in_pool_range()
74 paddr_t addr) in mm_find() argument
76 if (is_in_pool_range(p0, addr)) in mm_find()
77 return tee_mm_find(p0, addr); in mm_find()
78 if (is_in_pool_range(p1, addr)) in mm_find()
79 return tee_mm_find(p1, addr); in mm_find()
83 tee_mm_entry_t *nex_phys_mem_mm_find(paddr_t addr) in nex_phys_mem_mm_find() argument
85 return mm_find(nex_core_pool, nex_ta_pool, addr); in nex_phys_mem_mm_find()
190 tee_mm_entry_t *phys_mem_mm_find(paddr_t addr) in phys_mem_mm_find() argument
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