Searched refs:MUX_PLL3 (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/include/dt-bindings/clock/ |
| H A D | stm32mp13-clksrc.h | 87 #define MUX_PLL3 4 macro
151 #define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0)
152 #define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
153 #define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2)
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| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp13.c | 460 MUXRDY_CFG(MUX_PLL3, RCC_RCK3SELR, 0, 2, GATE_PLL3SRCRDY),
918 CLK_PLL_CFG(PLL3_ID, PLL_800, GATE_PLL3, MUX_PLL3, RCC_PLL3CR),
2101 0, RCC_PLL3CR, GATE_PLL3, MUX_PLL3);
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