Searched refs:GICR_ISENABLER0 (Results 1 – 1 of 1) sorted by relevance
78 #define GICR_ISENABLER0 (GICR_SGI_BASE_OFFSET + 0x100) macro305 io_write32(gicr_base + GICR_ISENABLER0, gd->per_cpu_enable); in gicv3_sync_redist_config()1069 io_write32(gicr_base + GICR_ISENABLER0, gd->per_cpu_enable); in gic_op_enable()