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Searched refs:CLK_SET_PARENT_GATE (Results 1 – 8 of 8) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dat91_usb.c105 clk->flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in _at91sam9x5_clk_register_usb()
H A Dat91_audio_pll.c346 clk->flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91_clk_register_audio_pll_pad()
377 clk->flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91_clk_register_audio_pll_pmc()
H A Dat91_programmable.c154 clk->flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91_clk_register_programmable()
H A Dsama7g5_clk.c206 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,
226 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,
246 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,
255 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,
275 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,
H A Dat91_generated.c173 clk->flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; in at91_clk_register_generated()
H A Dat91_main.c305 clk->flags = CLK_SET_PARENT_GATE; in at91_clk_register_sam9x5_main()
/optee_os/core/include/drivers/
H A Dclk.h16 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ macro
/optee_os/core/drivers/clk/
H A Dclk.c342 if (clk->flags & CLK_SET_PARENT_GATE && clk_is_enabled_no_lock(clk)) { in clk_set_parent()