Searched refs:BIT64 (Results 1 – 20 of 20) sorted by relevance
14 #define SCTLR_M BIT64(0)15 #define SCTLR_A BIT64(1)16 #define SCTLR_C BIT64(2)17 #define SCTLR_SA BIT64(3)18 #define SCTLR_I BIT64(12)19 #define SCTLR_ENDB BIT64(13)20 #define SCTLR_WXN BIT64(19)21 #define SCTLR_SPAN BIT64(23)22 #define SCTLR_ENDA BIT64(27)23 #define SCTLR_ENIB BIT64(30)[all …]
212 #define FFA_MEMORY_HANDLE_HYPERVISOR_BIT BIT64(63)213 #define FFA_MEMORY_HANDLE_SECURE_BIT BIT64(45)214 #define FFA_MEMORY_HANDLE_NON_SECURE_BIT BIT64(44)
104 #define PAR64_PA_MASK (BIT64(28) - 1)
171 return pa <= (BIT64(core_mmu_arm64_get_pa_width()) - 1); in core_mmu_check_max_pa()173 return pa <= (BIT64(40) - 1); in core_mmu_check_max_pa()206 return va < BIT64(core_mmu_get_va_width()); in core_mmu_va_is_valid()
194 return pa <= (BIT64(RISCV_MMU_PA_WIDTH) - 1); in core_mmu_check_max_pa()205 return va < BIT64(core_mmu_get_va_width()); in core_mmu_va_is_valid()217 uint64_t msb = BIT64(RISCV_MMU_VA_WIDTH - 1); in core_mmu_va_is_valid()
68 #define CSR_XIE_SIE BIT64(IRQ_XSOFT)69 #define CSR_XIE_TIE BIT64(IRQ_XTIMER)70 #define CSR_XIE_EIE BIT64(IRQ_XEXT)78 #define CSR_XCAUSE_INTR_FLAG BIT64(__riscv_xlen - 1)
33 #define BM_SGT_V2_F BIT64(BP_SGT_V2_F)35 #define BM_SGT_V2_IVP BIT64(BP_SGT_V2_IVP)
12 #define SOTP_ECC_ERR_DETECT BIT64(63)
220 ((vaddr_t)va & (BIT64(PAR_PA_SHIFT) - 1)); in arch_va2pa_helper()236 base_addr ^= BIT64(va_width - iteration_count); in arch_aslr_base_addr()
109 #define GP BIT64(50) /* Guarded Page, Aarch64 FEAT_BTI */1081 assert(max_va < BIT64(CFG_LPAE_ADDR_SPACE_BITS)); in core_init_mmu()1420 *size = BIT64(L1_XLAT_ADDRESS_SHIFT); in core_mmu_get_user_va_range()
32 ((BIT64(TL_REG_CONVENTION_VER_SHIFT_64)) - 1)) | \
272 vaddr_t va_width_msb = BIT64(RISCV_MMU_VA_WIDTH - 1); in core_mmu_pgt_get_va_base()725 const vaddr_t va_width_msb = BIT64(va_width - 1); in arch_aslr_base_addr()730 base_addr ^= BIT64(va_width - iteration_count); in arch_aslr_base_addr()984 *size = BIT64(CORE_MMU_VPN2_SHIFT); in core_mmu_get_user_va_range()989 *size = BIT64(CORE_MMU_VPN1_SHIFT); in core_mmu_get_user_va_range()
191 #define BIT64(nr) (1 << (nr))196 #define BIT64(nr) (UINT64_C(1) << (nr)) macro
999 va += BIT64(tbl_info.shift); in dump_xlat_table()1249 return paddr > BIT64(core_mmu_get_va_width()) / 2; in place_tee_ram_at_top()1870 pa += BIT64(tbl_info->shift); in set_region()1999 block_size = BIT64(tbl_info.shift); in core_mmu_map_region()2410 granule = BIT64(tbl_info.shift); in core_mmu_add_mapping()2513 paddr_t mask = BIT64(ti.shift) - 1; in check_pa_matches_va()
178 pa += BIT64(ti->shift); in set_pa_range()
162 uint64_t mask = BIT64(hash % 64) | in resolve_sym_helper()163 BIT64((hash >> h->bloom_shift) % 64); in resolve_sym_helper()
90 #define GICR_TYPER_LAST BIT64(4)794 mask |= BIT64(GICC_SGI_IRM_BIT); in gic_it_raise_sgi()
42 #define QM_SQC_VFT_VALID BIT64(44)
507 if (sqe->out & BIT64(1)) { in hpre_ecc_verify_get_result()
1895 nvb->pending |= BIT64(nvb->do_bottom_half_value); in notif_send_async()1920 BIT64(nvb->do_bottom_half_value)); in notif_send_async()