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Searched refs:AT91_PMC_PLL_CTRL0 (Results 1 – 3 of 3) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dclk-sam9x60-pll.c142 io_setbits32(regmap + AT91_PMC_PLL_CTRL0, in sam9x60_frac_pll_set()
171 io_clrbits32(frac->core.base + AT91_PMC_PLL_CTRL0, in sam9x60_frac_pll_unprepare()
250 io_setbits32(regmap + AT91_PMC_PLL_CTRL0, in sam9x60_frac_pll_set_rate_chg()
286 io_clrsetbits32(regmap + AT91_PMC_PLL_CTRL0, in sam9x60_div_pll_set_div()
311 val = io_read32(regmap + AT91_PMC_PLL_CTRL0); in sam9x60_div_pll_set()
337 io_clrbits32(regmap + AT91_PMC_PLL_CTRL0, core->layout->endiv_mask); in sam9x60_div_pll_unprepare()
384 val = io_read32(regmap + AT91_PMC_PLL_CTRL0); in sam9x60_div_pll_set_rate_chg()
521 val = io_read32(pmc->base + AT91_PMC_PLL_CTRL0); in sam9x60_clk_register_div_pll()
H A Dat91_pmc.h41 #define AT91_PMC_PLL_CTRL0 0x0C macro
/optee_os/core/drivers/pm/sam/
H A Dpm_suspend.S681 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
698 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
701 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
710 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
712 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
763 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
771 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]