Searched refs:rwcfg (Results 1 – 2 of 2) sorted by relevance
34 const struct socfpga_sdram_rw_mgr_config *rwcfg; variable139 ratio = rwcfg->mem_dq_per_read_dqs / in phy_mgr_initialize()140 rwcfg->mem_virtual_groups_per_read_dqs; in phy_mgr_initialize()143 param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1; in phy_mgr_initialize()144 param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1; in phy_mgr_initialize()164 switch (rwcfg->mem_number_of_ranks) { in set_rank_and_odt_mask()171 if (rwcfg->mem_number_of_cs_per_dimm == 1) { in set_rank_and_odt_mask()313 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, in scc_mgr_set_dqs_io_in_delay()320 rwcfg->mem_dq_per_write_dqs + 1 + dm, in scc_mgr_set_dm_in_delay()331 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, in scc_mgr_set_dqs_out1_delay()[all …]
10 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \11 / rwcfg->mem_if_write_dqs_width)12 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \13 / rwcfg->mem_if_write_dqs_width)15 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \16 / rwcfg->mem_if_write_dqs_width)17 #define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)