Lines Matching refs:rwcfg
34 const struct socfpga_sdram_rw_mgr_config *rwcfg; variable
139 ratio = rwcfg->mem_dq_per_read_dqs / in phy_mgr_initialize()
140 rwcfg->mem_virtual_groups_per_read_dqs; in phy_mgr_initialize()
143 param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1; in phy_mgr_initialize()
144 param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1; in phy_mgr_initialize()
164 switch (rwcfg->mem_number_of_ranks) { in set_rank_and_odt_mask()
171 if (rwcfg->mem_number_of_cs_per_dimm == 1) { in set_rank_and_odt_mask()
313 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, in scc_mgr_set_dqs_io_in_delay()
320 rwcfg->mem_dq_per_write_dqs + 1 + dm, in scc_mgr_set_dm_in_delay()
331 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, in scc_mgr_set_dqs_out1_delay()
338 rwcfg->mem_dq_per_write_dqs + 1 + dm, in scc_mgr_set_dm_out1_delay()
381 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_set_all_ranks()
445 const int ratio = rwcfg->mem_if_read_dqs_width / in scc_mgr_set_oct_out1_delay()
446 rwcfg->mem_if_write_dqs_width; in scc_mgr_set_oct_out1_delay()
502 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_zero_all()
504 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in scc_mgr_zero_all()
515 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { in scc_mgr_zero_all()
557 const int ratio = rwcfg->mem_if_read_dqs_width / in scc_mgr_load_dqs_for_write_group()
558 rwcfg->mem_if_write_dqs_width; in scc_mgr_load_dqs_for_write_group()
581 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_zero_group()
584 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { in scc_mgr_zero_group()
628 for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) { in scc_mgr_apply_group_dq_in_delay()
644 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { in scc_mgr_apply_group_dq_out1_delay()
686 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) in scc_mgr_apply_group_all_out_delay_add()
735 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_apply_group_all_out_delay_add_all_ranks()
756 writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); in set_jump_as_return()
811 writel(rwcfg->idle_loop1, in delay_for_n_mem_clocks()
814 writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | in delay_for_n_mem_clocks()
823 writel(rwcfg->idle_loop2, in delay_for_n_mem_clocks()
826 writel(rwcfg->idle_loop2, in delay_for_n_mem_clocks()
830 writel(rwcfg->idle_loop2, in delay_for_n_mem_clocks()
884 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { in rw_mgr_mem_load_user()
890 writel(rwcfg->precharge_all, grpaddr); in rw_mgr_mem_load_user()
896 if ((rwcfg->mem_address_mirroring >> r) & 0x1) { in rw_mgr_mem_load_user()
898 writel(rwcfg->mrs2_mirr, grpaddr); in rw_mgr_mem_load_user()
901 writel(rwcfg->mrs3_mirr, grpaddr); in rw_mgr_mem_load_user()
904 writel(rwcfg->mrs1_mirr, grpaddr); in rw_mgr_mem_load_user()
910 writel(rwcfg->mrs2, grpaddr); in rw_mgr_mem_load_user()
913 writel(rwcfg->mrs3, grpaddr); in rw_mgr_mem_load_user()
916 writel(rwcfg->mrs1, grpaddr); in rw_mgr_mem_load_user()
925 writel(rwcfg->zqcl, grpaddr); in rw_mgr_mem_load_user()
971 rwcfg->init_reset_0_cke_0); in rw_mgr_mem_initialize()
993 rwcfg->init_reset_1_cke_0); in rw_mgr_mem_initialize()
1000 rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset, in rw_mgr_mem_initialize()
1012 rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1); in rw_mgr_mem_handoff()
1076 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; in rw_mgr_mem_calibrate_write_test_issue()
1077 writel(rwcfg->lfsr_wr_rd_dm_bank_0_data, in rw_mgr_mem_calibrate_write_test_issue()
1079 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1082 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1; in rw_mgr_mem_calibrate_write_test_issue()
1083 writel(rwcfg->lfsr_wr_rd_bank_0_data, in rw_mgr_mem_calibrate_write_test_issue()
1085 writel(rwcfg->lfsr_wr_rd_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1098 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1099 writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs, in rw_mgr_mem_calibrate_write_test_issue()
1102 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1103 writel(rwcfg->lfsr_wr_rd_bank_0_dqs, in rw_mgr_mem_calibrate_write_test_issue()
1121 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1122 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1125 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1126 writel(rwcfg->lfsr_wr_rd_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1148 writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait, in rw_mgr_mem_calibrate_write_test_issue()
1151 writel(rwcfg->lfsr_wr_rd_bank_0_wait, in rw_mgr_mem_calibrate_write_test_issue()
1177 rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_write_test()
1179 const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs / in rw_mgr_mem_calibrate_write_test()
1180 rwcfg->mem_virtual_groups_per_write_dqs; in rw_mgr_mem_calibrate_write_test()
1193 for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1; in rw_mgr_mem_calibrate_write_test()
1200 rwcfg->mem_virtual_groups_per_write_dqs + vg, in rw_mgr_mem_calibrate_write_test()
1243 (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2; in rw_mgr_mem_calibrate_read_test_patterns()
1245 rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_read_test_patterns()
1247 const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs / in rw_mgr_mem_calibrate_read_test_patterns()
1248 rwcfg->mem_virtual_groups_per_read_dqs; in rw_mgr_mem_calibrate_read_test_patterns()
1263 writel(rwcfg->guaranteed_read, in rw_mgr_mem_calibrate_read_test_patterns()
1267 writel(rwcfg->guaranteed_read_cont, in rw_mgr_mem_calibrate_read_test_patterns()
1271 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; in rw_mgr_mem_calibrate_read_test_patterns()
1277 writel(rwcfg->guaranteed_read, in rw_mgr_mem_calibrate_read_test_patterns()
1288 writel(rwcfg->clear_dqs_enable, addr + (group << 2)); in rw_mgr_mem_calibrate_read_test_patterns()
1314 rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_read_load_patterns()
1327 writel(rwcfg->guaranteed_write_wait0, in rw_mgr_mem_calibrate_read_load_patterns()
1332 writel(rwcfg->guaranteed_write_wait1, in rw_mgr_mem_calibrate_read_load_patterns()
1337 writel(rwcfg->guaranteed_write_wait2, in rw_mgr_mem_calibrate_read_load_patterns()
1342 writel(rwcfg->guaranteed_write_wait3, in rw_mgr_mem_calibrate_read_load_patterns()
1345 writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_read_load_patterns()
1372 const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_read_test()
1392 writel(rwcfg->read_b2b_wait1, in rw_mgr_mem_calibrate_read_test()
1396 writel(rwcfg->read_b2b_wait2, in rw_mgr_mem_calibrate_read_test()
1407 writel(rwcfg->read_b2b, in rw_mgr_mem_calibrate_read_test()
1410 writel(rwcfg->mem_if_read_dqs_width * in rw_mgr_mem_calibrate_read_test()
1411 rwcfg->mem_virtual_groups_per_read_dqs - 1, in rw_mgr_mem_calibrate_read_test()
1416 writel(rwcfg->read_b2b, in rw_mgr_mem_calibrate_read_test()
1420 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; in rw_mgr_mem_calibrate_read_test()
1435 writel(rwcfg->read_b2b, addr + in rw_mgr_mem_calibrate_read_test()
1437 rwcfg->mem_virtual_groups_per_read_dqs + in rw_mgr_mem_calibrate_read_test()
1441 tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs / in rw_mgr_mem_calibrate_read_test()
1442 rwcfg->mem_virtual_groups_per_read_dqs; in rw_mgr_mem_calibrate_read_test()
1450 writel(rwcfg->clear_dqs_enable, addr + (group << 2)); in rw_mgr_mem_calibrate_read_test()
1982 const u32 ratio = rwcfg->mem_if_read_dqs_width / in search_stop_check()
1983 rwcfg->mem_if_write_dqs_width; in search_stop_check()
1986 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in search_stop_check()
1987 rwcfg->mem_dq_per_read_dqs; in search_stop_check()
2041 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in search_left_edge()
2042 rwcfg->mem_dq_per_read_dqs; in search_left_edge()
2152 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in search_right_edge()
2153 rwcfg->mem_dq_per_read_dqs; in search_right_edge()
2179 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; in search_right_edge()
2270 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in get_window_mid_index()
2271 rwcfg->mem_dq_per_read_dqs; in get_window_mid_index()
2321 const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in center_dq_windows()
2322 rwcfg->mem_dq_per_read_dqs; in center_dq_windows()
2401 int32_t left_edge[rwcfg->mem_dq_per_read_dqs]; in rw_mgr_mem_calibrate_vfifo_center()
2402 int32_t right_edge[rwcfg->mem_dq_per_read_dqs]; in rw_mgr_mem_calibrate_vfifo_center()
2418 for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) { in rw_mgr_mem_calibrate_vfifo_center()
2452 rwcfg->mem_dq_per_read_dqs + i, in rw_mgr_mem_calibrate_vfifo_center()
2457 rwcfg->mem_dq_per_read_dqs + i, in rw_mgr_mem_calibrate_vfifo_center()
2583 (rwcfg->mem_dq_per_read_dqs - 1); in rw_mgr_mem_calibrate_dqs_enable_calibration()
2590 for (r = 0; r < rwcfg->mem_number_of_ranks; in rw_mgr_mem_calibrate_dqs_enable_calibration()
2593 i < rwcfg->mem_dq_per_read_dqs; in rw_mgr_mem_calibrate_dqs_enable_calibration()
2616 for (r = 0; r < rwcfg->mem_number_of_ranks; in rw_mgr_mem_calibrate_dqs_enable_calibration()
2650 rank_bgn < rwcfg->mem_number_of_ranks; in rw_mgr_mem_calibrate_dq_dqs_centering()
2954 int left_edge[rwcfg->mem_dq_per_write_dqs]; in rw_mgr_mem_calibrate_writes_center()
2955 int right_edge[rwcfg->mem_dq_per_write_dqs]; in rw_mgr_mem_calibrate_writes_center()
2974 (rwcfg->mem_dq_per_write_dqs << 2)); in rw_mgr_mem_calibrate_writes_center()
2983 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { in rw_mgr_mem_calibrate_writes_center()
3144 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { in mem_precharge_and_activate()
3149 writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | in mem_precharge_and_activate()
3153 writel(rwcfg->activate_0_and_1_wait1, in mem_precharge_and_activate()
3157 writel(rwcfg->activate_0_and_1_wait2, in mem_precharge_and_activate()
3161 writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | in mem_precharge_and_activate()
3218 for (r = 0; r < rwcfg->mem_number_of_ranks; in mem_skip_calibrate()
3224 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in mem_skip_calibrate()
3262 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { in mem_skip_calibrate()
3272 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in mem_skip_calibrate()
3310 const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width / in mem_calibrate()
3311 rwcfg->mem_if_write_dqs_width; in mem_calibrate()
3328 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in mem_calibrate()
3365 < rwcfg->mem_if_write_dqs_width; write_group++, in mem_calibrate()
3366 write_test_bgn += rwcfg->mem_dq_per_write_dqs) { in mem_calibrate()
3386 read_test_bgn += rwcfg->mem_dq_per_read_dqs) { in mem_calibrate()
3405 rank_bgn < rwcfg->mem_number_of_ranks; in mem_calibrate()
3435 read_test_bgn += rwcfg->mem_dq_per_read_dqs) { in mem_calibrate()
3697 writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) | in initialize_tracking()
3698 (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0), in initialize_tracking()
3701 writel(rwcfg->mem_if_read_dqs_width, in initialize_tracking()
3705 writel((rwcfg->refresh_all << 24) | (1000 << 0), in initialize_tracking()
3721 rwcfg = socfpga_get_sdram_rwmgr_config(); in sdram_calibration_full()
3749 rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm, in sdram_calibration_full()
3750 rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs, in sdram_calibration_full()
3751 rwcfg->mem_virtual_groups_per_read_dqs, in sdram_calibration_full()
3752 rwcfg->mem_virtual_groups_per_write_dqs); in sdram_calibration_full()
3755 rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width, in sdram_calibration_full()
3756 rwcfg->mem_data_width, rwcfg->mem_data_mask_width, in sdram_calibration_full()