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Searched refs:reg_out (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-vx855.c85 u_int32_t reg_out; in vx855gpio_direction_input() local
97 reg_out = inl(vg->io_gpo); in vx855gpio_direction_input()
98 reg_out |= gpio_o_bit(nr - NR_VX855_GPInO); in vx855gpio_direction_input()
99 outl(reg_out, vg->io_gpo); in vx855gpio_direction_input()
135 u_int32_t reg_out; in vx855gpio_set() local
142 reg_out = inl(vg->io_gpo); in vx855gpio_set()
145 reg_out |= gpo_o_bit(nr - NR_VX855_GPI); in vx855gpio_set()
147 reg_out &= ~gpo_o_bit(nr - NR_VX855_GPI); in vx855gpio_set()
150 reg_out |= gpio_o_bit(nr - NR_VX855_GPInO); in vx855gpio_set()
152 reg_out &= ~gpio_o_bit(nr - NR_VX855_GPInO); in vx855gpio_set()
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H A Dgpio-max732x.c146 uint8_t reg_out[2]; member
211 uint8_t reg_out; in max732x_gpio_set_mask() local
216 reg_out = (off > 7) ? chip->reg_out[1] : chip->reg_out[0]; in max732x_gpio_set_mask()
217 reg_out = (reg_out & ~mask) | (val & mask); in max732x_gpio_set_mask()
219 ret = max732x_writeb(chip, is_group_a(chip, off), reg_out); in max732x_gpio_set_mask()
225 chip->reg_out[1] = reg_out; in max732x_gpio_set_mask()
227 chip->reg_out[0] = reg_out; in max732x_gpio_set_mask()
335 msg = (chip->irq_mask << 8) | chip->reg_out[0]; in max732x_irq_update_mask()
340 msg = chip->irq_mask | chip->reg_out[0]; in max732x_irq_update_mask()
689 ret = max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]); in max732x_probe()
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/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu540c.c45 void *reg_out; member
82 ctx->reg_out = mpp_calloc(JpegV540cStatus, 1); in hal_jpege_v540c_init()
112 MPP_FREE(ctx->reg_out); in hal_jpege_v540c_deinit()
234 JpegV540cStatus *reg_out = ctx->reg_out; in hal_jpege_v540c_start() local
275 cfg1.reg = &reg_out->hw_status; in hal_jpege_v540c_start()
285 cfg1.reg = &reg_out->st; in hal_jpege_v540c_start()
307 JpegV540cStatus *elem = (JpegV540cStatus *)ctx->reg_out; in hal_jpege_vepu540c_status_check()
349 JpegV540cStatus *elem = (JpegV540cStatus *)ctx->reg_out; in hal_jpege_v540c_wait()
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/jpegd/
H A Dhal_jpegd_rkv.c707 JpegRegSet *reg_out = ctx->regs; in hal_jpegd_rkv_wait() local
721 mpp_log_f("read regs[%d]=0x%08x\n", i, ((RK_U32*)reg_out)[i]); in hal_jpegd_rkv_wait()
725 jpegd_dbg_hal("decode one frame in cycles: %d\n", reg_out->reg39_perf_working_cnt); in hal_jpegd_rkv_wait()
727 if (!reg_out->reg1_int.dec_irq || !reg_out->reg1_int.dec_rdy_sta in hal_jpegd_rkv_wait()
728 || reg_out->reg1_int.dec_bus_sta || reg_out->reg1_int.dec_error_sta in hal_jpegd_rkv_wait()
729 || reg_out->reg1_int.dec_timeout_sta in hal_jpegd_rkv_wait()
730 || reg_out->reg1_int.dec_buf_empty_sta) { in hal_jpegd_rkv_wait()
731 mpp_err("decode result: failed, irq 0x%08x\n", ((RK_U32 *)reg_out)[1]); in hal_jpegd_rkv_wait()
761 memset(&reg_out->reg1_int, 0, sizeof(RK_U32)); in hal_jpegd_rkv_wait()
H A Dhal_jpegd_vdpu1.c957 JpegRegSet *reg_out = JpegHalCtx->regs; in hal_jpegd_vdpu1_wait() local
967 if (reg_out->reg1_interrupt.sw_dec_bus_int) { in hal_jpegd_vdpu1_wait()
969 } else if (reg_out->reg1_interrupt.sw_dec_error_int) { in hal_jpegd_vdpu1_wait()
978 } else if (reg_out->reg1_interrupt.sw_dec_timeout) { in hal_jpegd_vdpu1_wait()
980 } else if (reg_out->reg1_interrupt.sw_dec_buffer_int) { in hal_jpegd_vdpu1_wait()
982 } else if (reg_out->reg1_interrupt.sw_dec_irq) { in hal_jpegd_vdpu1_wait()
1019 memset(&reg_out->reg1_interrupt, 0, sizeof(RK_U32)); in hal_jpegd_vdpu1_wait()
H A Dhal_jpegd_vdpu2.c942 JpegRegSet *reg_out = JpegHalCtx->regs; in hal_jpegd_vdpu2_wait() local
952 if (reg_out->reg55_Interrupt.sw_dec_bus_int) { in hal_jpegd_vdpu2_wait()
954 } else if (reg_out->reg55_Interrupt.sw_dec_error_int) { in hal_jpegd_vdpu2_wait()
956 } else if (reg_out->reg55_Interrupt.sw_dec_timeout) { in hal_jpegd_vdpu2_wait()
958 } else if (reg_out->reg55_Interrupt.sw_dec_buffer_int) { in hal_jpegd_vdpu2_wait()
960 } else if (reg_out->reg55_Interrupt.sw_dec_irq) { in hal_jpegd_vdpu2_wait()
996 memset(&reg_out->reg55_Interrupt, 0, sizeof(RK_U32)); in hal_jpegd_vdpu2_wait()
/OK3568_Linux_fs/kernel/arch/powerpc/kvm/
H A Dbook3s_paired_singles.c491 int reg_out, int reg_in1, int reg_in2, in kvmppc_ps_three_in() argument
519 kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out)); in kvmppc_ps_three_in()
530 func(&vcpu->arch.fp.fpscr, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3); in kvmppc_ps_three_in()
533 ps1_in1, ps1_in2, ps1_in3, qpr[reg_out]); in kvmppc_ps_three_in()
539 int reg_out, int reg_in1, int reg_in2, in kvmppc_ps_two_in() argument
568 kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out)); in kvmppc_ps_two_in()
581 qpr[reg_out] = ps1_out; in kvmppc_ps_two_in()
584 ps1_in1, ps1_in2, qpr[reg_out]); in kvmppc_ps_two_in()
591 int reg_out, int reg_in, in kvmppc_ps_one_in() argument
609 kvm_cvt_fd(&ps0_out, &VCPU_FPR(vcpu, reg_out)); in kvmppc_ps_one_in()
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/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu2.c378 M2vdVdpu2Reg* reg_out = (M2vdVdpu2Reg * )ctx->regs; in hal_m2vd_vdpu2_wait() local
388 RK_U32 *p_reg = (RK_U32*)&reg_out; in hal_m2vd_vdpu2_wait()
394 if (reg_out->sw55.dec_error_int | reg_out->sw55.dec_buffer_int) { in hal_m2vd_vdpu2_wait()
400 mpp_log("mpp_device_wait_reg return interrupt:%08x", reg_out->sw55); in hal_m2vd_vdpu2_wait()
H A Dhal_m2vd_vdpu1.c305 M2vdVdpu1Reg_t* reg_out = (M2vdVdpu1Reg_t * )ctx->regs; in hal_m2vd_vdpu1_wait() local
311 if (reg_out->sw01.dec_error_int | reg_out->sw01.dec_buffer_int) { in hal_m2vd_vdpu1_wait()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c75 void *reg_out; member
634 ctx->reg_out = mpp_calloc(H265eV541IoctlOutputElem, 1); in hal_h265e_v541_init()
690 MPP_FREE(ctx->reg_out); in hal_h265e_v541_deinit()
1729 H265eV541IoctlOutputElem *reg_out = (H265eV541IoctlOutputElem *)ctx->reg_out; in hal_h265e_v540_start() local
1787 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540_start()
1797 cfg1.reg = &reg_out->st_bsl; in hal_h265e_v540_start()
1819 stream_len += reg_out->st_bsl.bs_lgth; in hal_h265e_v540_start()
1820 fb->qp_sum += reg_out->st_sse_qp.qp_sum; in hal_h265e_v540_start()
1821 fb->out_strm_size += reg_out->st_bsl.bs_lgth; in hal_h265e_v540_start()
1822 fb->sse_sum += reg_out->st_sse_l32.sse_l32 + in hal_h265e_v540_start()
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H A Dhal_h265e_vepu580.c91 void *reg_out[MAX_TILE_NUM]; member
1374 MPP_FREE(ctx->reg_out[i]); in hal_h265e_v580_deinit()
1455 ctx->reg_out[i] = mpp_calloc(H265eV580StatusElem, 1); in hal_h265e_v580_init()
2074 …PP_RET hal_h265e_v580_send_regs(MppDev dev, H265eV580RegSet *hw_regs, H265eV580StatusElem *reg_out) in hal_h265e_v580_send_regs() argument
2175 cfg1.reg = &reg_out->hw_status; in hal_h265e_v580_send_regs()
2185 cfg1.reg = &reg_out->st; in hal_h265e_v580_send_regs()
2727 H265eV580StatusElem *reg_out = (H265eV580StatusElem *)ctx->reg_out[k]; in hal_h265e_v580_start() local
2775 hal_h265e_v580_send_regs(ctx->dev, hw_regs, reg_out); in hal_h265e_v580_start()
2793 stream_len += reg_out->st.bs_lgth_l32; in hal_h265e_v580_start()
2794 fb->qp_sum += reg_out->st.qp_sum; in hal_h265e_v580_start()
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H A Dhal_h265e_vepu540c.c72 void *reg_out[MAX_TITLE_NUM]; member
531 ctx->reg_out[i] = mpp_calloc(H265eV540cStatusElem, 1); in hal_h265e_v540c_init()
577 MPP_FREE(ctx->reg_out[i]); in hal_h265e_v540c_deinit()
1293 H265eV540cStatusElem *reg_out = (H265eV540cStatusElem *)ctx->reg_out[0]; in hal_h265e_v540c_start() local
1386 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540c_start()
1396 cfg1.reg = &reg_out->st; in hal_h265e_v540c_start()
1422 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out[0]; in vepu540c_h265_set_feedback()
1519 H265eV540cStatusElem *elem = (H265eV540cStatusElem *)ctx->reg_out; in hal_h265e_v540c_wait()
H A Dhal_h265e_vepu580_tune.c482 H265eV580StatusElem *elem = (H265eV580StatusElem *)ctx->reg_out[i]; in vepu580_h265e_tune_stat_update()
/OK3568_Linux_fs/kernel/drivers/net/wireless/marvell/libertas/
H A Dif_spi.c152 __le16 reg_out = cpu_to_le16(reg | IF_SPI_WRITE_OPERATION_MASK); in spu_write() local
168 reg_trans.tx_buf = &reg_out; in spu_write()
169 reg_trans.len = sizeof(reg_out); in spu_write()
206 __le16 reg_out = cpu_to_le16(reg | IF_SPI_READ_OPERATION_MASK); in spu_read() local
226 reg_trans.tx_buf = &reg_out; in spu_read()
227 reg_trans.len = sizeof(reg_out); in spu_read()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c78 RK_U32 reg_out[VDPU34x_TOTAL_REG_CNT]; member
936 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out)); in hal_avs2d_rkv_start()
937 rd_cfg.reg = reg_ctx->reg_out; in hal_avs2d_rkv_start()
938 rd_cfg.size = sizeof(reg_ctx->reg_out); in hal_avs2d_rkv_start()
1085 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]); in hal_avs2d_rkv_wait()
H A Dhal_avs2d_vdpu382.c78 RK_U32 reg_out[VDPU382_TOTAL_REG_CNT]; member
1011 memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out)); in hal_avs2d_vdpu382_start()
1012 rd_cfg.reg = reg_ctx->reg_out; in hal_avs2d_vdpu382_start()
1013 rd_cfg.size = sizeof(reg_ctx->reg_out); in hal_avs2d_vdpu382_start()
1160 fprintf(fp_reg, "%08x\n", reg_ctx->reg_out[i]); in hal_avs2d_vdpu382_wait()
/OK3568_Linux_fs/kernel/sound/pci/emu10k1/
H A Demufx.c1194 int reg_in, int reg_out) in snd_emu10k1_audigy_dsp_convert_32_to_2x16() argument
1202 A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2)); in snd_emu10k1_audigy_dsp_convert_32_to_2x16()
1203 A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000); in snd_emu10k1_audigy_dsp_convert_32_to_2x16()