Searched refs:pllar (Results 1 – 6 of 6) sorted by relevance
79 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); in at91_clock_init()116 void at91_plla_init(u32 pllar) in at91_plla_init() argument120 writel(pllar, &pmc->pllar); in at91_plla_init()
25 void at91_plla_init(u32 pllar);26 void at91_pllb_init(u32 pllar);
40 u32 pllar; /* 0x28 PLL A Register */ member
137 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); in at91_clock_init()203 void at91_plla_init(u32 pllar) in at91_plla_init() argument207 writel(pllar, &pmc->pllar); in at91_plla_init()
126 u32 pllar; member183 regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar); in pmc_suspend()223 if (pmc_cache.pllar != tmp) in pmc_resume()
129 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); in at91_clock_init()