Searched refs:pic_wd8_m1 (Results 1 – 15 of 15) sorted by relevance
184 regs->reg0272_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in vepu540c_set_jpeg_reg()
543 RK_U32 pic_wd8_m1 : 11; member
460 RK_U32 pic_wd8_m1 : 11; member
248 RK_U32 pic_wd8_m1 : 9; member
379 RK_U32 pic_wd8_m1 : 11; member
460 regs->reg012.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu541_prep()1303 RK_U32 pic_temp = ((regs->reg012.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in setup_vepu541_me()
454 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu540c_prep()1222 RK_S32 pic_wdt_align = ((base_regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 2; in calc_cime_parameter()
357 RK_U32 pic_wd8_m1 : 11; member
699 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()
131 RK_U32 pic_wd8_m1 : 9; member
467 RK_U32 pic_wd8_m1 : 11; member
1364 pic_cime_temp = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in vepu540_h265_set_me_ram()1373 tile_ctu_endx = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 - 1; in vepu540_h265_set_me_ram()1586 regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v541_gen_regs()
973 RK_S32 pic_wdt_align = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 31) / 32 ; in vepu540c_h265_set_me_regs()1209 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v540c_gen_regs()
218 RK_U32 pic_wd64 = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64; in vepu580_h265_set_me_ram()238 tile_ctu_endx = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 - 1; in vepu580_h265_set_me_ram()2579 reg_base->reg0196_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v580_gen_regs()
350 RK_U32 pic_wd8_m1 : 11; member