it6161_hdmi_tx_write (reference) in projects: OK3568_Linux_fs

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Searched refs:it6161_hdmi_tx_write (Results 1 – 2 of 2) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A D	ite-it6161.c	1202 static int it6161_hdmi_tx_write(struct it6161 *it6161, unsigned int reg_addr, in it6161_hdmi_tx_write() function 1398 …it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK1, ~(B_TX_AUDIO_OVFLW_MASK \| B_TX_DDC_FIFO_ERR_MASK \| … in it6161_hdmi_tx_int_mask_enable() 1399 …it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK2, ~(B_TX_AUTH_FAIL_MASK \| B_TX_AUTH_DONE_MASK \| B_TX_… in it6161_hdmi_tx_int_mask_enable() 1400 it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK3, ~B_TX_VIDSTABLE_MASK); in it6161_hdmi_tx_int_mask_enable() 1411 it6161_hdmi_tx_write(it6161, table[i].offset, in it6161_hdmi_tx_write_table() 1750 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC \| B_TX_MASTERHOST); in it6161_hdmi_tx_clear_ddc_fifo() 1751 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_FIFO_CLR); in it6161_hdmi_tx_clear_ddc_fifo() 1758 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC\|B_TX_MASTERHOST); in it6161_hdmi_tx_generate_ddc_sclk() 1759 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD,CMD_GEN_SCLCLK); in it6161_hdmi_tx_generate_ddc_sclk() 1782 it6161_hdmi_tx_write(it6161, 0x91, vsync_rising_at_h_2nd >> 4); in hdmi_tx_generate_blank_timing() [all …]
H A D	ite_it6161_hdmi_tx.h	1238 #define hdmitx_ENABLE_NULL_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_NULL_CTRL,B_TX_ENABL… 1239 #define hdmitx_ENABLE_ACP_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ACP_CTRL,B_TX_ENABLE… 1240 #define hdmitx_ENABLE_ISRC1_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ISRC1_CTRL,B_TX_ENAB… 1241 #define hdmitx_ENABLE_ISRC2_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_ISRC2_CTRL,B_TX_ENAB… 1242 #define hdmitx_ENABLE_AVI_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL,B_T… 1243 #define hdmitx_ENABLE_AUD_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_AUD_INFOFRM_CTRL,B_T… 1244 #define hdmitx_ENABLE_SPD_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_SPD_INFOFRM_CTRL,B_T… 1245 #define hdmitx_ENABLE_MPG_INFOFRM_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_MPG_INFOFRM_CTRL,B_T… 1246 #define hdmitx_ENABLE_GeneralPurpose_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_NULL_CTRL,B_TX_ENA… 1247 #define hdmitx_DISABLE_VSDB_PKT() { it6161_hdmi_tx_write(it6161, REG_TX_3D_INFO_CTRL,0); } [all …]