Searched refs:dss_dphy0_cfg_clk (Results 1 – 3 of 3) sorted by relevance
889 ret = clk_prepare_enable(ctx->dss_dphy0_cfg_clk); in dsi_encoder_enable_sub()1233 ctx->dss_dphy0_cfg_clk = devm_clk_get(&pdev->dev, "clk_txdphy0_cfg"); in dsi_parse_dt()1234 if (IS_ERR(ctx->dss_dphy0_cfg_clk)) { in dsi_parse_dt()1236 return PTR_ERR(ctx->dss_dphy0_cfg_clk); in dsi_parse_dt()1239 ret = clk_set_rate(ctx->dss_dphy0_cfg_clk, DEFAULT_MIPI_CLK_RATE); in dsi_parse_dt()1248 clk_get_rate(ctx->dss_dphy0_cfg_clk)); in dsi_parse_dt()
59 struct clk *dss_dphy0_cfg_clk; member
245 clk_disable_unprepare(ctx->dss_dphy0_cfg_clk); in dsi_encoder_disable()