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Searched refs:dpcd_data (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Ddp.c662 u8 dpcd_data; in tegra_dc_dp_init_max_link_cfg() local
665 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
668 link_cfg->max_lane_count = dpcd_data & DP_MAX_LANE_COUNT_MASK; in tegra_dc_dp_init_max_link_cfg()
669 link_cfg->tps3_supported = (dpcd_data & in tegra_dc_dp_init_max_link_cfg()
673 (dpcd_data & DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? in tegra_dc_dp_init_max_link_cfg()
676 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
679 link_cfg->downspread = (dpcd_data & DP_MAX_DOWNSPREAD_VAL_0_5_PCT) ? in tegra_dc_dp_init_max_link_cfg()
699 ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
704 (dpcd_data & DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES) ? in tegra_dc_dp_init_max_link_cfg()
707 (dpcd_data & DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES) ? in tegra_dc_dp_init_max_link_cfg()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_dp.c3263 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data, in dp_wa_power_up_0010FA() argument
3272 dpcd_data, length); in dp_wa_power_up_0010FA()
3273 link->dpcd_caps.dpcd_rev.raw = dpcd_data[ in dp_wa_power_up_0010FA()
3306 uint8_t dpcd_data; in dpcd_read_sink_ext_caps() local
3311 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK) in dpcd_read_sink_ext_caps()
3314 link->dpcd_sink_ext_caps.raw = dpcd_data; in dpcd_read_sink_ext_caps()
3323 uint8_t dpcd_data[16]; in retrieve_link_cap() local
3342 memset(dpcd_data, '\0', sizeof(dpcd_data)); in retrieve_link_cap()
3377 dpcd_data, in retrieve_link_cap()
3378 sizeof(dpcd_data)); in retrieve_link_cap()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c9085 uint8_t dpcd_data; in is_dp_capable_without_timing_msa() local
9093 &dpcd_data, in is_dp_capable_without_timing_msa()
9094 sizeof(dpcd_data))) { in is_dp_capable_without_timing_msa()
9095 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; in is_dp_capable_without_timing_msa()
9197 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; in amdgpu_dm_set_psr_caps() local
9204 dpcd_data, sizeof(dpcd_data))) { in amdgpu_dm_set_psr_caps()
9205 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0]; in amdgpu_dm_set_psr_caps()
9207 if (dpcd_data[0] == 0) { in amdgpu_dm_set_psr_caps()