Searched refs:ddrdqsclk (Results 1 – 2 of 2) sorted by relevance
220 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, in cm_basic_init()221 &clock_manager_base->sdr_pll.ddrdqsclk); in cm_basic_init()269 ret = cm_write_with_phase(cfg->ddrdqsclk, in cm_basic_init()270 (u32)&clock_manager_base->sdr_pll.ddrdqsclk, in cm_basic_init()397 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); in cm_get_sdram_clk_hz()
40 u32 ddrdqsclk; member87 u32 ddrdqsclk; member