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Searched refs:ddrdqclk (Results 1 – 2 of 2) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c226 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, in cm_basic_init()
227 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
282 ret = cm_write_with_phase(cfg->ddrdqclk, in cm_basic_init()
283 (u32)&clock_manager_base->sdr_pll.ddrdqclk, in cm_basic_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h42 u32 ddrdqclk; member
89 u32 ddrdqclk; member