Searched refs:clk_state (Results 1 – 9 of 9) sorted by relevance
40 if (sched->clk_state == SLIM_CLK_ACTIVE) { in slim_ctrl_clk_pause()63 if (sched->clk_state == SLIM_CLK_PAUSED && ctrl->wakeup) in slim_ctrl_clk_pause()66 sched->clk_state = SLIM_CLK_ACTIVE; in slim_ctrl_clk_pause()73 if (ctrl->sched.clk_state == SLIM_CLK_PAUSED) { in slim_ctrl_clk_pause()89 sched->clk_state = SLIM_CLK_ENTERING_PAUSE; in slim_ctrl_clk_pause()112 sched->clk_state = SLIM_CLK_ACTIVE; in slim_ctrl_clk_pause()114 sched->clk_state = SLIM_CLK_PAUSED; in slim_ctrl_clk_pause()
120 if (ctrl->sched.clk_state == SLIM_CLK_ENTERING_PAUSE && in slim_do_transfer()128 if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) { in slim_do_transfer()130 ctrl->sched.clk_state, ret); in slim_do_transfer()
498 if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) { in slim_device_report_present()500 ctrl->sched.clk_state, ret); in slim_device_report_present()
178 enum slim_clk_state clk_state; member
288 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info() local292 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; in dce_clock_read_integrated_info()296 clk_state = DM_PP_CLOCKS_STATE_LOW; in dce_clock_read_integrated_info()300 clk_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce_clock_read_integrated_info()304 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; in dce_clock_read_integrated_info()308 clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info()316 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = in dce_clock_read_integrated_info()
363 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info() local367 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; in dce_clock_read_integrated_info()371 clk_state = DM_PP_CLOCKS_STATE_LOW; in dce_clock_read_integrated_info()375 clk_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce_clock_read_integrated_info()379 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; in dce_clock_read_integrated_info()383 clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info()390 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = in dce_clock_read_integrated_info()
53 struct pinctrl_state *clk_state; member733 if (IS_ERR_OR_NULL(pdm->pinctrl) || !pdm->clk_state) in rockchip_pdm_pinctrl_select_clk_state()748 pinctrl_select_state(pdm->pinctrl, pdm->clk_state); in rockchip_pdm_pinctrl_select_clk_state()973 pdm->clk_state = pinctrl_lookup_state(pdm->pinctrl, "clk"); in rockchip_pdm_probe()974 if (IS_ERR(pdm->clk_state)) { in rockchip_pdm_probe()975 pdm->clk_state = NULL; in rockchip_pdm_probe()
121 struct pinctrl_state *clk_state; member214 if (IS_ERR_OR_NULL(i2s_tdm->pinctrl) || !i2s_tdm->clk_state) in rockchip_i2s_tdm_pinctrl_select_clk_state()217 pinctrl_select_state(i2s_tdm->pinctrl, i2s_tdm->clk_state); in rockchip_i2s_tdm_pinctrl_select_clk_state()2651 i2s_tdm->clk_state = pinctrl_lookup_state(i2s_tdm->pinctrl, "clk"); in rockchip_i2s_tdm_probe()2652 if (IS_ERR(i2s_tdm->clk_state)) { in rockchip_i2s_tdm_probe()2653 i2s_tdm->clk_state = NULL; in rockchip_i2s_tdm_probe()
165 enum s3c_nand_clk_state clk_state; member233 if (info->clk_state == CLOCK_ENABLE) { in s3c2410_nand_clk_set_state()241 info->clk_state = new_state; in s3c2410_nand_clk_set_state()