Searched refs:cl_value (Results 1 – 2 of 2) sorted by relevance
| /OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_static.c | 216 u32 cl_value; in ddr3_tip_read_leveling_static_config() local
239 cl_value = tm->interface_params[first_active_if].cas_l; in ddr3_tip_read_leveling_static_config()
241 ("cl_value 0x%x\n", cl_value)); in ddr3_tip_read_leveling_static_config()
244 cl_value = cas_latency_table[speed_bin_index].cl_val[frequency]; in ddr3_tip_read_leveling_static_config()
247 cl_value, speed_bin_index)); in ddr3_tip_read_leveling_static_config()
327 (rd_sample_dly[0] + cl_value) + (rd_sample_dly[1] << 8), in ddr3_tip_read_leveling_static_config()
334 rd_ready_del[0] + (rd_ready_del[1] << 8) + cl_value, in ddr3_tip_read_leveling_static_config()
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| H A D | ddr3_training.c | 87 u32 if_id, u32 cl_value, u32 cwl_value);
313 u32 cl_value = 0, cwl_val = 0; in hws_ddr3_tip_init_controller() local
501 cl_value = in hws_ddr3_tip_init_controller()
509 cl_value, cwl_val)); in hws_ddr3_tip_init_controller()
512 ((cl_mask_table[cl_value] & 0x1) << 2) | in hws_ddr3_tip_init_controller()
513 ((cl_mask_table[cl_value] & 0xe) << 3); in hws_ddr3_tip_init_controller()
551 cl_value, cwl_val); in hws_ddr3_tip_init_controller()
1224 u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0, in ddr3_tip_freq_set() local
1276 cl_value = in ddr3_tip_freq_set()
1281 cl_value = in ddr3_tip_freq_set()
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