Searched refs:ZYNQ_GPIO_DIRM_OFFSET (Results 1 – 2 of 2) sorted by relevance
72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) macro268 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_input()270 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_input()288 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_output()290 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_output()314 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_get_function()
72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) macro324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()388 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_get_direction()684 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_save_context()716 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_restore_context()