Searched refs:XWT_CSR0_EWDT1_MASK (Results 1 – 2 of 2) sorted by relevance
15 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/ macro35 if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK)) in hw_watchdog_reset()46 writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0); in hw_watchdog_disable()61 writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK), in hw_watchdog_init()
29 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ macro66 iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), in xilinx_wdt_start()85 iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), in xilinx_wdt_stop()