1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2011-2013 Xilinx Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <asm/microblaze_intc.h> 10*4882a593Smuzhiyun #include <asm/processor.h> 11*4882a593Smuzhiyun #include <watchdog.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */ 14*4882a593Smuzhiyun #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */ 15*4882a593Smuzhiyun #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/ 16*4882a593Smuzhiyun #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct watchdog_regs { 19*4882a593Smuzhiyun u32 twcsr0; /* 0x0 */ 20*4882a593Smuzhiyun u32 twcsr1; /* 0x4 */ 21*4882a593Smuzhiyun u32 tbr; /* 0x8 */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun static struct watchdog_regs *watchdog_base = 25*4882a593Smuzhiyun (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR; 26*4882a593Smuzhiyun hw_watchdog_reset(void)27*4882a593Smuzhiyunvoid hw_watchdog_reset(void) 28*4882a593Smuzhiyun { 29*4882a593Smuzhiyun u32 reg; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Read the current contents of TCSR0 */ 32*4882a593Smuzhiyun reg = readl(&watchdog_base->twcsr0); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Clear the watchdog WDS bit */ 35*4882a593Smuzhiyun if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK)) 36*4882a593Smuzhiyun writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0); 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun hw_watchdog_disable(void)39*4882a593Smuzhiyunvoid hw_watchdog_disable(void) 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun u32 reg; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Read the current contents of TCSR0 */ 44*4882a593Smuzhiyun reg = readl(&watchdog_base->twcsr0); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0); 47*4882a593Smuzhiyun writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun puts("Watchdog disabled!\n"); 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun hw_watchdog_isr(void * arg)52*4882a593Smuzhiyunstatic void hw_watchdog_isr(void *arg) 53*4882a593Smuzhiyun { 54*4882a593Smuzhiyun hw_watchdog_reset(); 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun hw_watchdog_init(void)57*4882a593Smuzhiyunvoid hw_watchdog_init(void) 58*4882a593Smuzhiyun { 59*4882a593Smuzhiyun int ret; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK), 62*4882a593Smuzhiyun &watchdog_base->twcsr0); 63*4882a593Smuzhiyun writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ, 66*4882a593Smuzhiyun hw_watchdog_isr, NULL); 67*4882a593Smuzhiyun if (ret) 68*4882a593Smuzhiyun puts("Watchdog IRQ registration failed."); 69*4882a593Smuzhiyun } 70