Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (Results 1 – 1 of 1) sorted by relevance
181 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1) macro264 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; in pcie_phy_enable()