Searched refs:TRCVICTLR (Results 1 – 3 of 3) sorted by relevance
90 WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCVICTLR, TRCVICTLR_SSSTATUS | BIT(0)),
418 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); in etm4_enable_hw()846 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR); in etm4_disable_perf()1615 state->trcvictlr = etm4x_read32(csa, TRCVICTLR); in __etm4_cpu_save()1744 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); in __etm4_cpu_restore()
41 #define TRCVICTLR 0x080 macro195 CASE_##op((val), TRCVICTLR) \