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Searched refs:SSPP_VIG3 (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_top.c141 status->sspp[SSPP_VIG3] = (value >> 10) & 0x3; in dpu_hw_get_danger_status()
238 status->sspp[SSPP_VIG3] = (value >> 10) & 0x1; in dpu_hw_get_safe_status()
H A Ddpu_hw_ctl.c150 case SSPP_VIG3: in dpu_hw_ctl_get_bitmask_sspp()
411 case SSPP_VIG3: in dpu_hw_ctl_setup_blendstage()
H A Ddpu_hw_mdss.h112 SSPP_VIG3, enumerator
H A Ddpu_hw_interrupts.c389 { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2},
390 { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
H A Ddpu_hw_catalog.c348 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_ctl.c298 case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage); in mdp_ctl_blend_mask()
321 case SSPP_VIG3: return MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3; in mdp_ctl_blend_ext_mask()
449 case SSPP_VIG3: return MDP5_CTL_FLUSH_VIG3; in mdp_ctl_flush_mask_pipe()
H A Dmdp5_cfg.c196 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
433 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
H A Dmdp5.xml.h77 SSPP_VIG3 = 9, enumerator
547 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]); in __offset_PIPE()
H A Dmdp5_kms.c727 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator