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/OK3568_Linux_fs/buildroot/package/spandsp/
H A D0001-configure.ac-fix-AVX-SSE-and-MMX-options.patch4 Subject: [PATCH] configure.ac: fix AVX, SSE and MMX options
6 AVX, SSE and MMX options are broken since
9 For example, when the user enables SSE, it will also enable MMX and the
53 AC_DEFINE([SPANDSP_USE_SSE], [1], [Use the SSE instruction set (i386 and x86_64 only).])
/OK3568_Linux_fs/yocto/poky/meta/recipes-bsp/grub/files/
H A D0001-Disable-mfpmath-sse-as-well-when-SSE-is-disabled.patch4 Subject: [PATCH] Disable -mfpmath=sse as well when SSE is disabled
19 conftest.c:1:0: error: SSE instruction set disabled, using 387
/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dverify_cpu.S124 jz .Lverify_cpu_no_longmode # only try to force SSE on AMD
127 btr $15,%eax # enable SSE
/OK3568_Linux_fs/yocto/meta-openembedded/meta-oe/recipes-devtools/yasm/
H A Dyasm_git.bb1 SUMMARY = "x86 (SSE) assembler supporting NASM and GAS-syntaxes"
/OK3568_Linux_fs/yocto/poky/meta/conf/machine/include/x86/
H A Dtune-i686.inc12 # Set x86 target arch to i686, so that glibc enables SSE optimised memcpy, etc.
H A Dtune-core2.inc3 # Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
H A Dtune-corei7.inc3 # Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
/OK3568_Linux_fs/yocto/poky/meta/recipes-multimedia/gstreamer/
H A Dgstreamer1.0-plugins-common.inc16 # bytecode to SIMD instructions for various architectures (currently SSE, MMX,
/OK3568_Linux_fs/buildroot/package/libfreeimage/
H A D0002-fix-cpuid-x86.patch17 // Helper functions for gcc + SSE enabled
/OK3568_Linux_fs/yocto/poky/meta/recipes-core/systemd/systemd/
H A D0001-shared-json-allow-json_variant_dump-to-return-an-err.patch39 fputc('\n', f); /* In case of SSE add a second newline */
/OK3568_Linux_fs/kernel/arch/x86/crypto/
H A Dcrct10dif-pcl-asm_64.S2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
H A Dchacha-ssse3-x86_64.S231 # the state matrix in SSE registers four times. As we need some scratch
236 # which allows us to do XOR in SSE registers. 8/16-bit word rotation is
/OK3568_Linux_fs/yocto/poky/meta/recipes-bsp/grub/
H A Dgrub2.inc17 file://0001-Disable-mfpmath-sse-as-well-when-SSE-is-disabled.patch \
/OK3568_Linux_fs/kernel/drivers/scsi/aic7xxx/
H A Daic7xxx_pci.c591 #define SSE 0x40 macro
1942 if (status1 & SSE) { in ahc_pci_intr()
1963 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { in ahc_pci_intr()
H A Daic79xx.reg1144 field SSE 0x40
1162 field SSE 0x40
1179 field SSE 0x40
1195 field SSE 0x40
1212 field SSE 0x40
1227 field SSE 0x40
1244 field SSE 0x40
H A Daic79xx_pci.c732 #define SSE 0x40 macro
H A Daic79xx_reg.h_shipped1309 #define SSE 0x40
/OK3568_Linux_fs/external/mpp/debian/
H A Dchangelog14 * [h264e]: add SSE parameter check
/OK3568_Linux_fs/buildroot/package/rocksdb/
H A D0001-build_tools-build_detect_platform-fix-C-tests.patch261 echo "warning: USE_SSE specified but compiler could not use SSE intrinsics, disabling" >&2
/OK3568_Linux_fs/yocto/poky/meta/recipes-core/gettext/gettext-minimal-0.21/aclocal/
H A Dhost-cpu-c-abi.m442 dnl MMX, SSE, SSE2, 3DNow! etc.) are not frequently used. If your
/OK3568_Linux_fs/external/rknpu2/examples/3rdparty/opencv/opencv-linux-armhf/share/OpenCV/licenses/
H A Dlibjpeg-turbo-README.md278 - The SSE/SSE2 floating point DCT implementation in libjpeg-turbo is ever so
/OK3568_Linux_fs/kernel/arch/x86/
H A DKconfig.cpu251 of SSE and tells gcc to treat the CPU as a 686.
/OK3568_Linux_fs/external/rknpu2/examples/3rdparty/opencv/OpenCV-android-sdk/sdk/etc/licenses/
H A Dlibjpeg-turbo-README.md278 - The SSE/SSE2 floating point DCT implementation in libjpeg-turbo is ever so
/OK3568_Linux_fs/external/rknpu2/examples/3rdparty/opencv/opencv-linux-aarch64/share/OpenCV/licenses/
H A Dlibjpeg-turbo-README.md278 - The SSE/SSE2 floating point DCT implementation in libjpeg-turbo is ever so
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/share/info/
H A Dgcc.info26125 SSE instruction set support.
26129 with MMX, SSE and SSE2 instruction set support. Used by
26134 Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set
26138 Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2
26143 extensions, MMX, SSE, SSE2 and SSE3 instruction set support.
26146 Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3
26150 Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2,
26155 Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2,
26160 Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2,
26165 Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2,
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