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Searched refs:SPRN_L1CSR0 (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/arch/powerpc/kernel/
H A Dcpu_setup_fsl_booke.S30 mfspr r0, SPRN_L1CSR0
36 mtspr SPRN_L1CSR0, r0 /* Disable */
40 mtspr SPRN_L1CSR0, r0 /* Invalidate */
42 1: mfspr r0, SPRN_L1CSR0
49 mtspr SPRN_L1CSR0, r0 /* Enable */
/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S116 mtspr SPRN_L1CSR0,r2
118 mfspr r3,SPRN_L1CSR0
124 mtspr SPRN_L1CSR0,r3
127 mfspr r3,SPRN_L1CSR0
H A Dstart.S792 mtspr SPRN_L1CSR0,r2
794 mfspr r3,SPRN_L1CSR0
800 mtspr SPRN_L1CSR0,r3
803 mfspr r3,SPRN_L1CSR0
/OK3568_Linux_fs/kernel/arch/powerpc/mm/nohash/
H A Dfsl_booke.c227 tmp = mfspr(SPRN_L1CSR0); in flush_instruction_cache()
229 mtspr(SPRN_L1CSR0, tmp); in flush_instruction_cache()
/OK3568_Linux_fs/kernel/arch/powerpc/kvm/
H A De500_emulate.c248 case SPRN_L1CSR0: in kvmppc_core_emulate_mtspr_e500()
378 case SPRN_L1CSR0: in kvmppc_core_emulate_mfspr_e500()
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h485 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ macro
733 #define L1CSR0 SPRN_L1CSR0
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dreg_booke.h173 #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ macro