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Searched refs:SET_MEDIUM_FREQ_MASK_BIT (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip.h27 #define SET_MEDIUM_FREQ_MASK_BIT 0x00000010 macro
H A Dddr3_a38x.c398 SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT | in ddr3_tip_init_a38x_silicon()
H A Dddr3_training.c72 u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |
2074 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) { in ddr3_tip_ddr3_training_main_flow()
H A Dddr3_debug.c379 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) { in ddr3_tip_print_log()