Searched refs:RK3328_PRE_PLL_PCLK_DIV_D (Results 1 – 1 of 1) sorted by relevance
167 #define RK3328_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) macro805 RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d)); in inno_hdmi_phy_rk3328_clk_set_rate()