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Searched refs:QCA953X_PLL_DDR_CONFIG_REG (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S146 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
159 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
162 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
H A Dclk.c65 val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG); in get_clocks()
/OK3568_Linux_fs/kernel/arch/mips/ath79/
H A Dclock.c382 pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG); in qca953x_clocks_init()
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h421 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 macro
/OK3568_Linux_fs/kernel/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h353 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 macro