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Searched refs:PcieLaneCount (Results 1 – 25 of 25) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/inc/
H A Dsmu9_driver_if.h237 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
H A Dsmu7_discrete.h212 uint8_t PcieLaneCount; member
H A Dsmu71_discrete.h154 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
H A Dsmu73_discrete.h130 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
H A Dsmu74_discrete.h158 uint8_t PcieLaneCount; member
H A Dsmu11_driver_if.h453 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
H A Dsmu72_discrete.h145 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
H A Dsmu75_discrete.h168 uint8_t PcieLaneCount; member
H A Dsmu11_driver_if_sienna_cichlid.h729 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
H A Dsmu11_driver_if_navi10.h626 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dsmu7_discrete.h212 uint8_t PcieLaneCount; member
H A Dci_dpm.c2621 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c524 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : in vega12_override_pcie_parameters()
525 pp_table->PcieLaneCount[i]; in vega12_override_pcie_parameters()
528 pp_table->PcieLaneCount[i]) { in vega12_override_pcie_parameters()
540 pp_table->PcieLaneCount[i] = pcie_width_arg; in vega12_override_pcie_parameters()
555 pp_table->PcieLaneCount[i] = pcie_width; in vega12_override_pcie_parameters()
H A Dvega20_hwmgr.c870 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : in vega20_override_pcie_parameters()
871 pp_table->PcieLaneCount[i]; in vega20_override_pcie_parameters()
874 pp_table->PcieLaneCount[i]) { in vega20_override_pcie_parameters()
886 pp_table->PcieLaneCount[i] = pcie_width_arg; in vega20_override_pcie_parameters()
901 pp_table->PcieLaneCount[i] = pcie_width; in vega20_override_pcie_parameters()
3460 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
H A Dvega10_hwmgr.c1546 if (pp_table->PcieLaneCount[i] > pcie_width) in vega10_override_pcie_parameters()
1547 pp_table->PcieLaneCount[i] = pcie_width; in vega10_override_pcie_parameters()
1553 pp_table->PcieLaneCount[i] = pcie_width; in vega10_override_pcie_parameters()
1571 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; in vega10_populate_smc_link_levels()
1584 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; in vega10_populate_smc_link_levels()
4694 lane_width = pptable->PcieLaneCount[i]; in vega10_print_clock_levels()
H A Dvega20_processpptables.c404 pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/inc/vega12/
H A Dsmu9_driver_if.h341 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c1889 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; in navi10_update_pcie_parameters()
1895 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? in navi10_update_pcie_parameters()
1896 pptable->PcieLaneCount[i] : pcie_width_cap); in navi10_update_pcie_parameters()
1907 if (pptable->PcieLaneCount[i] > pcie_width_cap) in navi10_update_pcie_parameters()
H A Dsienna_cichlid_ppt.c1717 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; in sienna_cichlid_update_pcie_parameters()
1725 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? in sienna_cichlid_update_pcie_parameters()
1726 pptable->PcieLaneCount[i] : in sienna_cichlid_update_pcie_parameters()
1739 if (pptable->PcieLaneCount[i] > pcie_width_cap) in sienna_cichlid_update_pcie_parameters()
2184 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); in sienna_cichlid_dump_pptable()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c583 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in vegam_populate_smc_link_level()
H A Dfiji_smumgr.c840 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in fiji_populate_smc_link_level()
H A Diceland_smumgr.c775 table->LinkLevel[i].PcieLaneCount = in iceland_populate_smc_link_level()
H A Dpolaris10_smumgr.c780 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in polaris10_populate_smc_link_level()
H A Dci_smumgr.c1007 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
H A Dtonga_smumgr.c518 table->LinkLevel[i].PcieLaneCount = in tonga_populate_smc_link_level()