Searched refs:PRR (Results 1 – 3 of 3) sorted by relevance
11 #define PRR 0xFF000044 macro18 return (readl(PRR) & 0x00007F00) >> 8; in rmobile_get_cpu_type()23 const u32 prr = readl(PRR); in rmobile_get_cpu_rev_integer()33 const u32 prr = readl(PRR); in rmobile_get_cpu_rev_fraction()
39 Partial Reconfiguration Region (PRR)41 * A PRR is a specific section of a FPGA reserved for reconfiguration.42 * A base (or static) FPGA image may create a set of PRR's that later may44 * The size and specific location of each PRR is fixed.45 * The connections at the edge of each PRR are fixed. The image that is loaded46 into a PRR must fit and must use a subset of the region's connections.52 * An FPGA image that is designed to be loaded into a PRR. There may be53 any number of personas designed to fit into a PRR, but only one at at time101 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be152 base FPGA region. The "Full Reconfiguration to add PRR's" example below shows[all …]
43 (a) flash new firmware that disables SPI (set PRR.2, and disable pullups