Searched refs:PANEL_POWER_CYCLE_DELAY_MASK (Results 1 – 6 of 6) sorted by relevance
335 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) macro
171 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()220 …REP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_RO… in intel_lvds_pps_init_hw()
6964 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state()7168 …REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_RO… in intel_dp_init_panel_power_sequencer_registers()
202 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) macro
2055 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> in cdv_intel_dp_init()
5059 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) macro