Searched refs:LPDDR5 (Results 1 – 5 of 5) sorted by relevance
81 4. LPDDR5 4个通道使用不同的write vref。83 6. LPDDR5 cavref更新为36%。133 | 3 | 重要 | 优化LPDDR5性能 | LPDDR5模式下tWTR计算错误导致效率较差 | - …239 4. 开启LPDDR5 DMC功能。240 5. 支持LPDDR5 byte mode颗粒。250 | 4 | 重要 | 提高LPDDR5稳定性与性能 | 修正一些LPDDR5 timing配置，提高LPDDR5稳定性和性能。 | - |295 2. 添加LPDDR5变频补丁，支持行间变频。
81 4. LPDDR5 4 channels use different write vref values to improve stability.83 6. LPDDR5 cavref update to 36%.133 | 3 | important | improve LP5 performance | LPDDR5 timing tWTR calculate error lead to sl…239 4. Enable LPDDR5 DMC function.240 5. Support LPDDR5 byte mode DRAM.250 | 4 | important | Improve LPDDR5 stability and performance | Fix some LPDDR5 timing like rd2wr,…295 2. Add LPDDR5 DFS patches, support DFS between rows.
94 LPDDR5 = 9, enumerator372 if (info->dram_type == LPDDR5) { in rockchip_dfi_start_hardware_counter()390 else if (info->dram_type == LPDDR5) in rockchip_dfi_start_hardware_counter()444 else if (info->dram_type == LPDDR5) in rockchip_dfi_get_busier_ch()544 if (data->dram_type == LPDDR5) in rk3588_dfi_init()
18 LPDDR5 = 9, enumerator
401 else if (dram_type == LPDDR5) in dmc_fsp_probe()