1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_SDRAM_H 8*4882a593Smuzhiyun #define _ASM_ARCH_SDRAM_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun enum { 11*4882a593Smuzhiyun DDR4 = 0, 12*4882a593Smuzhiyun DDR2 = 2, 13*4882a593Smuzhiyun DDR3 = 3, 14*4882a593Smuzhiyun LPDDR2 = 5, 15*4882a593Smuzhiyun LPDDR3 = 6, 16*4882a593Smuzhiyun LPDDR4 = 7, 17*4882a593Smuzhiyun LPDDR4X = 8, 18*4882a593Smuzhiyun LPDDR5 = 9, 19*4882a593Smuzhiyun DDR5 = 10, 20*4882a593Smuzhiyun UNUSED = 0xFF 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct ddr_param { 24*4882a593Smuzhiyun u32 count; 25*4882a593Smuzhiyun u32 reserved; 26*4882a593Smuzhiyun u64 para[8]; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * sys_reg bitfield struct 31*4882a593Smuzhiyun * [31] row_3_4_ch1 32*4882a593Smuzhiyun * [30] row_3_4_ch0 33*4882a593Smuzhiyun * [29:28] chinfo 34*4882a593Smuzhiyun * [27] rank_ch1 35*4882a593Smuzhiyun * [26:25] col_ch1 36*4882a593Smuzhiyun * [24] bk_ch1 37*4882a593Smuzhiyun * [23:22] low bits of cs0_row_ch1 38*4882a593Smuzhiyun * [21:20] low bits of cs1_row_ch1 39*4882a593Smuzhiyun * [19:18] bw_ch1 40*4882a593Smuzhiyun * [17:16] dbw_ch1; 41*4882a593Smuzhiyun * [15:13] ddrtype 42*4882a593Smuzhiyun * [12] channelnum 43*4882a593Smuzhiyun * [11] rank_ch0 44*4882a593Smuzhiyun * [10:9] col_ch0, 45*4882a593Smuzhiyun * [8] bk_ch0 46*4882a593Smuzhiyun * [7:6] low bits of cs0_row_ch0 47*4882a593Smuzhiyun * [5:4] low bits of cs1_row_ch0 48*4882a593Smuzhiyun * [3:2] bw_ch0 49*4882a593Smuzhiyun * [1:0] dbw_ch0 50*4882a593Smuzhiyun * 51*4882a593Smuzhiyun * sys_reg1 bitfield struct 52*4882a593Smuzhiyun * [7] high bit of cs0_row_ch1 53*4882a593Smuzhiyun * [6] high bit of cs1_row_ch1 54*4882a593Smuzhiyun * [5] high bit of cs0_row_ch0 55*4882a593Smuzhiyun * [4] high bit of cs1_row_ch0 56*4882a593Smuzhiyun * [3:2] cs1_col_ch1 57*4882a593Smuzhiyun * [1:0] cs1_col_ch0 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define SYS_REG_DDRTYPE_SHIFT 13 60*4882a593Smuzhiyun #define SYS_REG_DDRTYPE_MASK 7 61*4882a593Smuzhiyun #define SYS_REG_NUM_CH_SHIFT 12 62*4882a593Smuzhiyun #define SYS_REG_NUM_CH_MASK 1 63*4882a593Smuzhiyun #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) 64*4882a593Smuzhiyun #define SYS_REG_ROW_3_4_MASK 1 65*4882a593Smuzhiyun #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) 66*4882a593Smuzhiyun #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) 67*4882a593Smuzhiyun #define SYS_REG_RANK_MASK 1 68*4882a593Smuzhiyun #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) 69*4882a593Smuzhiyun #define SYS_REG_COL_MASK 3 70*4882a593Smuzhiyun #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) 71*4882a593Smuzhiyun #define SYS_REG_BK_MASK 1 72*4882a593Smuzhiyun #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) 73*4882a593Smuzhiyun #define SYS_REG_CS0_ROW_MASK 3 74*4882a593Smuzhiyun #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) 75*4882a593Smuzhiyun #define SYS_REG_CS1_ROW_MASK 3 76*4882a593Smuzhiyun #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) 77*4882a593Smuzhiyun #define SYS_REG_BW_MASK 3 78*4882a593Smuzhiyun #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) 79*4882a593Smuzhiyun #define SYS_REG_DBW_MASK 3 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define SYS_REG1_VERSION_SHIFT 28 82*4882a593Smuzhiyun #define SYS_REG1_VERSION_MASK 0xf 83*4882a593Smuzhiyun #define SYS_REG1_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) 84*4882a593Smuzhiyun #define SYS_REG1_EXTEND_CS0_ROW_MASK 1 85*4882a593Smuzhiyun #define SYS_REG1_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2) 86*4882a593Smuzhiyun #define SYS_REG1_EXTEND_CS1_ROW_MASK 1 87*4882a593Smuzhiyun #define SYS_REG1_CS1_COL_SHIFT(ch) (0 + (ch) * 2) 88*4882a593Smuzhiyun #define SYS_REG1_CS1_COL_MASK 3 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Get sdram size decode from reg */ 91*4882a593Smuzhiyun size_t rockchip_sdram_size(phys_addr_t reg); 92*4882a593Smuzhiyun unsigned int get_page_size(void); 93*4882a593Smuzhiyun unsigned int get_ddr_bw(void); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Called by U-Boot board_init_r for Rockchip SoCs */ 96*4882a593Smuzhiyun int dram_init(void); 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Write ddr param to a known place for trustos */ 99*4882a593Smuzhiyun int rockchip_setup_ddr_param(struct ddr_param *info); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif 102